Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	105678991	15644	0	0
claim_transition_if_regwen_rd_A	105678991	1430	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105678991	15644	0	0
T19	443931	10	0	0
T24	46663	0	0	0
T38	0	1	0	0
T39	0	12	0	0
T51	38652	0	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	919	0	0	0
T81	187688	0	0	0
T82	30636	0	0	0
T83	2124	0	0	0
T84	15611	0	0	0
T85	238468	0	0	0
T86	18827	0	0	0
T129	0	2	0	0
T130	0	6	0	0
T131	0	6	0	0
T132	0	5	0	0
T133	0	2	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105678991	1430	0	0
T88	240342	0	0	0
T92	0	11	0	0
T96	0	22	0	0
T97	0	7	0	0
T103	0	3	0	0
T105	0	31	0	0
T129	166856	13	0	0
T133	0	16	0	0
T134	0	27	0	0
T135	0	2	0	0
T136	0	19	0	0
T137	6502	0	0	0
T138	52340	0	0	0
T139	1033	0	0	0
T140	22183	0	0	0
T141	28202	0	0	0
T142	34335	0	0	0
T143	37297	0	0	0
T144	24532	0	0	0