Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1815670	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2038728

1

T2

3138

T3

5

T4

13688

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3499962	1			T2	4662		T3	2		T4	26673
values[0x0]	176817	1			T2	533		T3	2		T4	225
values[0x1]	177619	1			T2	546		T3	6		T4	222

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1443094	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2411304

1

T2

3716

T3

7

T4

16390

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12425	1			T2	18		T4	112		T8	6
valid_sources[0x01]	13182	1			T2	17		T4	107		T8	9
valid_sources[0x02]	14822	1			T2	14		T4	89		T8	6
valid_sources[0x03]	12981	1			T2	2		T4	96		T8	4
valid_sources[0x04]	12193	1			T2	13		T4	108		T8	9
valid_sources[0x05]	12044	1			T2	20		T4	110		T8	7
valid_sources[0x06]	12153	1			T2	23		T4	90		T8	3
valid_sources[0x07]	11900	1			T2	21		T4	108		T8	2
valid_sources[0x08]	13870	1			T2	11		T4	134		T8	6
valid_sources[0x09]	12521	1			T2	20		T4	91		T8	5
valid_sources[0x0a]	12440	1			T2	38		T4	98		T8	11
valid_sources[0x0b]	12918	1			T2	7		T4	126		T8	4
valid_sources[0x0c]	13192	1			T2	12		T4	112		T8	4
valid_sources[0x0d]	12663	1			T2	11		T4	133		T8	4
valid_sources[0x0e]	14547	1			T2	30		T4	117		T8	11
valid_sources[0x0f]	15890	1			T2	26		T4	95		T8	4
valid_sources[0x10]	26718	1			T2	17		T4	112		T8	9
valid_sources[0x11]	12679	1			T2	21		T4	103		T8	5
valid_sources[0x12]	12245	1			T2	6		T4	114		T8	2
valid_sources[0x13]	12358	1			T2	9		T4	105		T8	4
valid_sources[0x14]	13829	1			T2	20		T4	125		T8	4
valid_sources[0x15]	13584	1			T2	23		T4	103		T8	3
valid_sources[0x16]	12421	1			T2	16		T4	127		T8	10
valid_sources[0x17]	11832	1			T2	8		T4	92		T8	2
valid_sources[0x18]	14954	1			T2	15		T4	123		T8	7
valid_sources[0x19]	14186	1			T2	58		T4	110		T8	6
valid_sources[0x1a]	74528	1			T2	37		T4	94		T8	6
valid_sources[0x1b]	12546	1			T2	15		T4	114		T8	7
valid_sources[0x1c]	14242	1			T2	19		T4	97		T8	5
valid_sources[0x1d]	14981	1			T2	8		T4	103		T8	5
valid_sources[0x1e]	13572	1			T2	49		T4	89		T8	9
valid_sources[0x1f]	14034	1			T2	1		T4	106		T8	4
valid_sources[0x20]	14067	1			T4	105		T8	5		T11	12
valid_sources[0x21]	28799	1			T2	15		T4	111		T8	5
valid_sources[0x22]	14198	1			T2	33		T4	100		T8	1
valid_sources[0x23]	11886	1			T2	18		T4	92		T8	8
valid_sources[0x24]	12735	1			T2	27		T4	102		T8	3
valid_sources[0x25]	12942	1			T2	19		T4	98		T8	5
valid_sources[0x26]	16193	1			T2	15		T4	113		T8	8
valid_sources[0x27]	11799	1			T2	38		T4	108		T8	7
valid_sources[0x28]	15260	1			T2	7		T4	128		T8	4
valid_sources[0x29]	11803	1			T2	13		T4	102		T8	5
valid_sources[0x2a]	12214	1			T2	35		T4	99		T8	9
valid_sources[0x2b]	16702	1			T2	42		T4	124		T8	9
valid_sources[0x2c]	12552	1			T2	21		T4	85		T8	7
valid_sources[0x2d]	12060	1			T2	4		T4	109		T8	3
valid_sources[0x2e]	12555	1			T2	21		T4	110		T8	5
valid_sources[0x2f]	24296	1			T2	12		T4	110		T8	6
valid_sources[0x30]	12667	1			T2	21		T4	105		T8	7
valid_sources[0x31]	12113	1			T2	11		T4	91		T8	5
valid_sources[0x32]	13364	1			T2	46		T4	94		T8	3
valid_sources[0x33]	14080	1			T2	18		T4	86		T8	5
valid_sources[0x34]	12956	1			T2	36		T4	116		T8	3
valid_sources[0x35]	12147	1			T2	33		T4	106		T8	7
valid_sources[0x36]	12880	1			T2	14		T4	90		T8	7
valid_sources[0x37]	14500	1			T2	12		T4	95		T8	5
valid_sources[0x38]	12775	1			T2	7		T4	96		T8	4
valid_sources[0x39]	12303	1			T2	26		T4	100		T8	6
valid_sources[0x3a]	14875	1			T2	29		T4	90		T8	8
valid_sources[0x3b]	14462	1			T2	41		T4	114		T8	14
valid_sources[0x3c]	12173	1			T2	54		T4	107		T8	6
valid_sources[0x3d]	12980	1			T2	18		T4	114		T8	6
valid_sources[0x3e]	13004	1			T2	17		T4	97		T8	6
valid_sources[0x3f]	12216	1			T2	29		T4	112		T8	7
valid_sources[0x40]	14709	1			T2	21		T4	100		T8	5
valid_sources[0x41]	12244	1			T2	44		T4	108		T8	2
valid_sources[0x42]	13001	1			T2	10		T4	91		T8	6
valid_sources[0x43]	11763	1			T4	110		T8	4		T11	8
valid_sources[0x44]	24346	1			T2	26		T4	90		T8	2
valid_sources[0x45]	13022	1			T2	37		T4	111		T8	8
valid_sources[0x46]	11943	1			T2	9		T4	119		T11	16
valid_sources[0x47]	12943	1			T2	24		T4	107		T8	5
valid_sources[0x48]	14619	1			T2	43		T4	93		T8	4
valid_sources[0x49]	25229	1			T2	32		T4	97		T8	8
valid_sources[0x4a]	12708	1			T2	17		T4	127		T8	5
valid_sources[0x4b]	12370	1			T2	2		T4	82		T8	6
valid_sources[0x4c]	12774	1			T2	5		T4	121		T8	3
valid_sources[0x4d]	13258	1			T2	36		T4	117		T8	9
valid_sources[0x4e]	12522	1			T2	21		T4	91		T8	7
valid_sources[0x4f]	13323	1			T2	12		T4	99		T8	8
valid_sources[0x50]	20597	1			T2	17		T4	105		T8	9
valid_sources[0x51]	12506	1			T2	27		T4	119		T8	10
valid_sources[0x52]	15012	1			T2	37		T4	98		T8	6
valid_sources[0x53]	12955	1			T2	30		T4	98		T8	2
valid_sources[0x54]	13961	1			T2	8		T4	101		T8	7
valid_sources[0x55]	12315	1			T2	12		T4	106		T8	5
valid_sources[0x56]	15208	1			T2	41		T4	104		T8	3
valid_sources[0x57]	12243	1			T2	3		T4	94		T8	9
valid_sources[0x58]	29914	1			T2	35		T4	112		T8	4
valid_sources[0x59]	14166	1			T2	37		T4	129		T8	3
valid_sources[0x5a]	12183	1			T2	24		T4	86		T8	7
valid_sources[0x5b]	12593	1			T2	10		T4	142		T8	5
valid_sources[0x5c]	45679	1			T2	20		T4	93		T8	10
valid_sources[0x5d]	12566	1			T2	30		T4	128		T8	4
valid_sources[0x5e]	37002	1			T2	18		T4	101		T8	8
valid_sources[0x5f]	13219	1			T2	38		T4	116		T11	11
valid_sources[0x60]	12819	1			T2	13		T4	115		T8	6
valid_sources[0x61]	12649	1			T2	23		T4	115		T8	11
valid_sources[0x62]	12310	1			T2	5		T4	85		T8	10
valid_sources[0x63]	12817	1			T2	42		T4	103		T8	6
valid_sources[0x64]	12588	1			T2	95		T4	107		T8	4
valid_sources[0x65]	47473	1			T2	21		T4	92		T8	3
valid_sources[0x66]	11835	1			T2	29		T4	104		T8	5
valid_sources[0x67]	14924	1			T2	30		T4	104		T8	4
valid_sources[0x68]	12141	1			T2	10		T4	131		T8	9
valid_sources[0x69]	12940	1			T2	29		T4	93		T8	7
valid_sources[0x6a]	23235	1			T2	5		T4	117		T8	5
valid_sources[0x6b]	12558	1			T2	13		T4	117		T8	8
valid_sources[0x6c]	13231	1			T2	44		T4	93		T8	3
valid_sources[0x6d]	12047	1			T2	12		T4	93		T8	8
valid_sources[0x6e]	12622	1			T2	5		T4	112		T8	6
valid_sources[0x6f]	15752	1			T2	28		T4	121		T8	4
valid_sources[0x70]	12827	1			T2	38		T4	134		T8	7
valid_sources[0x71]	12142	1			T2	3		T4	108		T8	7
valid_sources[0x72]	13823	1			T2	29		T4	106		T8	8
valid_sources[0x73]	12900	1			T2	24		T4	118		T8	5
valid_sources[0x74]	13224	1			T2	6		T4	100		T8	7
valid_sources[0x75]	13021	1			T2	23		T4	84		T8	4
valid_sources[0x76]	12549	1			T2	47		T4	121		T8	8
valid_sources[0x77]	12175	1			T2	15		T4	115		T8	5
valid_sources[0x78]	13829	1			T2	46		T4	90		T8	4
valid_sources[0x79]	12281	1			T2	4		T4	106		T8	3
valid_sources[0x7a]	12502	1			T2	15		T4	100		T8	4
valid_sources[0x7b]	20983	1			T2	6		T4	104		T8	9
valid_sources[0x7c]	12487	1			T2	26		T4	102		T8	10
valid_sources[0x7d]	12623	1			T2	24		T4	108		T8	12
valid_sources[0x7e]	13124	1			T2	42		T4	122		T8	5
valid_sources[0x7f]	12816	1			T2	18		T4	112		T8	7
valid_sources[0x80]	12302	1			T2	8		T4	117		T8	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1733377

1

T2

2198

T4

13312

T8

441

values[0x0]

all_enables

biggest_size

153217

1

T2

465

T3

2

T4

186

values[0x1]

all_enables

biggest_size

152134

1

T2

475

T3

3

T4

190