Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	117145317	13515	0	0
claim_transition_if_regwen_rd_A	117145317	2187	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117145317	13515	0	0
T12	979885	9	0	0
T16	0	4	0	0
T18	29819	0	0	0
T21	39120	0	0	0
T22	3755	0	0	0
T23	17094	0	0	0
T24	24789	0	0	0
T25	3443	0	0	0
T34	18634	0	0	0
T35	12821	0	0	0
T40	0	8	0	0
T41	0	1	0	0
T42	0	2	0	0
T87	0	2	0	0
T143	0	2	0	0
T144	0	2	0	0
T145	0	1	0	0
T146	0	10	0	0
T147	1431	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117145317	2187	0	0
T31	16999	0	0	0
T42	0	1	0	0
T87	111301	10	0	0
T111	0	34	0	0
T115	0	15	0	0
T116	0	62	0	0
T117	0	10	0	0
T119	0	14	0	0
T148	0	20	0	0
T149	0	5	0	0
T150	0	4	0	0
T151	27951	0	0	0
T152	6797	0	0	0
T153	2624	0	0	0
T154	39494	0	0	0
T155	32379	0	0	0
T156	44554	0	0	0
T157	781236	0	0	0
T158	724527	0	0	0