Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1779113	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2007933

1

T1

1142

T2

1293

T3

2770

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3433056	1			T1	1187		T2	1882		T3	2261
values[0x0]	176381	1			T1	341		T2	202		T3	1036
values[0x1]	177609	1			T1	331		T2	198		T3	1016

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1414313	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2372733

1

T1

1310

T2

1498

T3

3145

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12703	1			T1	7		T3	5		T9	5
valid_sources[0x01]	10652	1			T1	2		T3	47		T8	1
valid_sources[0x02]	10964	1			T1	2		T3	25		T8	1
valid_sources[0x03]	11333	1			T1	7		T3	20		T9	6
valid_sources[0x04]	11074	1			T1	4		T3	25		T8	1
valid_sources[0x05]	11004	1			T1	7		T3	1		T9	10
valid_sources[0x06]	11955	1			T1	8		T3	6		T8	1
valid_sources[0x07]	11342	1			T1	2		T3	85		T9	8
valid_sources[0x08]	12259	1			T1	7		T3	22		T9	8
valid_sources[0x09]	11290	1			T1	10		T3	15		T9	6
valid_sources[0x0a]	12112	1			T1	9		T3	2		T8	2
valid_sources[0x0b]	10789	1			T1	9		T3	3		T9	6
valid_sources[0x0c]	10754	1			T1	6		T3	11		T9	5
valid_sources[0x0d]	10678	1			T1	5		T3	32		T9	4
valid_sources[0x0e]	12695	1			T1	6		T3	27		T9	3
valid_sources[0x0f]	11205	1			T1	5		T3	8		T9	5
valid_sources[0x10]	10865	1			T1	5		T3	27		T9	3
valid_sources[0x11]	11109	1			T1	5		T3	24		T9	5
valid_sources[0x12]	25024	1			T1	6		T3	22		T9	5
valid_sources[0x13]	11494	1			T1	9		T3	31		T9	5
valid_sources[0x14]	13562	1			T1	5		T9	6		T10	1
valid_sources[0x15]	10967	1			T1	9		T3	9		T9	10
valid_sources[0x16]	11747	1			T1	6		T3	4		T9	11
valid_sources[0x17]	12871	1			T1	13		T3	12		T9	2
valid_sources[0x18]	11243	1			T1	7		T3	17		T9	8
valid_sources[0x19]	11037	1			T1	8		T3	6		T8	1
valid_sources[0x1a]	11365	1			T1	5		T3	30		T9	5
valid_sources[0x1b]	11886	1			T1	3		T3	4		T8	2
valid_sources[0x1c]	10799	1			T1	6		T3	28		T9	6
valid_sources[0x1d]	10789	1			T1	6		T3	6		T8	1
valid_sources[0x1e]	11550	1			T1	5		T3	15		T9	7
valid_sources[0x1f]	12455	1			T1	6		T3	19		T9	4
valid_sources[0x20]	10892	1			T1	7		T3	17		T8	2
valid_sources[0x21]	13076	1			T1	7		T3	9		T9	4
valid_sources[0x22]	10950	1			T1	12		T3	18		T9	2
valid_sources[0x23]	11769	1			T1	5		T8	1		T9	5
valid_sources[0x24]	41953	1			T1	2		T3	20		T9	7
valid_sources[0x25]	11171	1			T1	6		T3	18		T8	2
valid_sources[0x26]	13029	1			T1	9		T3	17		T9	2
valid_sources[0x27]	14218	1			T1	3		T3	2		T9	3
valid_sources[0x28]	11508	1			T1	5		T3	8		T8	1
valid_sources[0x29]	11008	1			T1	7		T3	25		T9	5
valid_sources[0x2a]	11713	1			T1	22		T3	15		T9	7
valid_sources[0x2b]	14150	1			T1	3		T3	23		T9	5
valid_sources[0x2c]	11019	1			T1	5		T3	22		T9	4
valid_sources[0x2d]	11865	1			T1	8		T3	29		T9	7
valid_sources[0x2e]	10860	1			T1	10		T3	18		T9	3
valid_sources[0x2f]	11219	1			T1	4		T3	3		T9	4
valid_sources[0x30]	11516	1			T1	8		T3	9		T8	1
valid_sources[0x31]	11233	1			T1	10		T3	25		T9	5
valid_sources[0x32]	11138	1			T1	7		T3	8		T9	7
valid_sources[0x33]	11009	1			T1	1		T3	20		T9	2
valid_sources[0x34]	10817	1			T1	7		T3	20		T9	7
valid_sources[0x35]	11312	1			T1	12		T3	8		T9	7
valid_sources[0x36]	10880	1			T1	3		T3	18		T9	5
valid_sources[0x37]	11808	1			T1	10		T3	29		T9	11
valid_sources[0x38]	11469	1			T1	5		T3	1		T9	3
valid_sources[0x39]	14656	1			T1	5		T3	20		T9	1
valid_sources[0x3a]	11191	1			T1	4		T3	14		T8	1
valid_sources[0x3b]	12969	1			T1	9		T3	22		T9	6
valid_sources[0x3c]	11105	1			T1	15		T3	25		T9	5
valid_sources[0x3d]	10849	1			T1	5		T3	7		T8	1
valid_sources[0x3e]	46496	1			T1	6		T3	7		T9	7
valid_sources[0x3f]	12826	1			T1	17		T3	6		T9	7
valid_sources[0x40]	16016	1			T1	8		T3	13		T9	11
valid_sources[0x41]	31484	1			T1	4		T3	7		T8	1
valid_sources[0x42]	10768	1			T1	6		T3	18		T9	4
valid_sources[0x43]	10762	1			T1	5		T3	37		T9	9
valid_sources[0x44]	12098	1			T1	7		T3	7		T9	14
valid_sources[0x45]	10700	1			T1	11		T3	11		T9	2
valid_sources[0x46]	10889	1			T1	10		T3	5		T9	10
valid_sources[0x47]	10997	1			T1	4		T3	17		T9	6
valid_sources[0x48]	18285	1			T1	8		T3	14		T9	4
valid_sources[0x49]	10750	1			T1	5		T3	23		T9	4
valid_sources[0x4a]	10923	1			T1	6		T3	35		T9	5
valid_sources[0x4b]	11195	1			T1	7		T3	15		T9	5
valid_sources[0x4c]	10985	1			T1	4		T3	18		T8	1
valid_sources[0x4d]	10845	1			T1	4		T3	13		T9	8
valid_sources[0x4e]	17400	1			T1	6		T3	20		T9	6
valid_sources[0x4f]	11117	1			T1	8		T3	6		T8	1
valid_sources[0x50]	11306	1			T1	6		T3	7		T9	5
valid_sources[0x51]	13022	1			T1	13		T3	5		T9	6
valid_sources[0x52]	11158	1			T1	10		T3	37		T8	1
valid_sources[0x53]	12645	1			T1	10		T3	8		T9	5
valid_sources[0x54]	13193	1			T1	9		T3	12		T9	4
valid_sources[0x55]	12674	1			T1	8		T3	2		T8	1
valid_sources[0x56]	12404	1			T1	11		T3	11		T9	2
valid_sources[0x57]	10851	1			T1	11		T3	7		T9	5
valid_sources[0x58]	10958	1			T1	4		T3	15		T9	5
valid_sources[0x59]	136289	1			T1	6		T3	25		T9	6
valid_sources[0x5a]	10904	1			T1	12		T3	22		T9	1
valid_sources[0x5b]	12195	1			T1	6		T3	24		T9	2
valid_sources[0x5c]	17450	1			T1	7		T3	21		T8	1
valid_sources[0x5d]	10971	1			T1	7		T3	17		T8	1
valid_sources[0x5e]	11218	1			T1	6		T9	7		T10	5
valid_sources[0x5f]	13112	1			T1	9		T3	3		T9	6
valid_sources[0x60]	12463	1			T1	8		T3	14		T9	6
valid_sources[0x61]	10932	1			T1	2		T3	14		T9	8
valid_sources[0x62]	11152	1			T1	5		T3	14		T9	4
valid_sources[0x63]	12446	1			T1	7		T3	21		T9	4
valid_sources[0x64]	11170	1			T1	3		T3	14		T9	10
valid_sources[0x65]	10627	1			T1	3		T3	13		T9	3
valid_sources[0x66]	12981	1			T1	5		T3	21		T9	10
valid_sources[0x67]	11200	1			T1	11		T3	16		T9	3
valid_sources[0x68]	11020	1			T1	6		T3	19		T9	11
valid_sources[0x69]	13877	1			T1	4		T3	20		T9	14
valid_sources[0x6a]	11568	1			T1	6		T3	22		T9	3
valid_sources[0x6b]	11968	1			T1	9		T3	46		T9	6
valid_sources[0x6c]	11332	1			T1	8		T3	8		T9	2
valid_sources[0x6d]	10914	1			T1	4		T3	3		T9	6
valid_sources[0x6e]	14392	1			T1	9		T3	41		T8	1
valid_sources[0x6f]	10886	1			T1	5		T3	4		T9	3
valid_sources[0x70]	13915	1			T1	7		T3	3		T9	3
valid_sources[0x71]	10928	1			T1	8		T3	32		T9	11
valid_sources[0x72]	93221	1			T1	2		T3	9		T9	7
valid_sources[0x73]	10891	1			T1	7		T3	8		T9	3
valid_sources[0x74]	13440	1			T1	4		T3	31		T8	2
valid_sources[0x75]	11002	1			T1	13		T3	16		T8	1
valid_sources[0x76]	10928	1			T1	1		T3	3		T9	5
valid_sources[0x77]	13731	1			T1	5		T3	22		T9	5
valid_sources[0x78]	10901	1			T1	12		T3	11		T9	6
valid_sources[0x79]	11207	1			T1	11		T3	23		T8	1
valid_sources[0x7a]	11253	1			T1	8		T3	3		T9	3
valid_sources[0x7b]	10960	1			T1	10		T3	33		T9	8
valid_sources[0x7c]	11332	1			T1	7		T3	8		T9	6
valid_sources[0x7d]	15044	1			T1	8		T3	90		T9	6
valid_sources[0x7e]	10606	1			T1	9		T3	47		T9	7
valid_sources[0x7f]	11482	1			T1	7		T3	65		T8	2
valid_sources[0x80]	12656	1			T1	8		T3	3		T9	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1702741

1

T1

562

T2

944

T3

984

values[0x0]

all_enables

biggest_size

152913

1

T1

299

T2

176

T3

902

values[0x1]

all_enables

biggest_size

152279

1

T1

281

T2

173

T3

884