Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	100.00	82.35	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	106955467	14904	0	0
claim_transition_if_regwen_rd_A	106955467	1610	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106955467	14904	0	0
T16	547036	1	0	0
T23	39955	0	0	0
T42	0	5	0	0
T44	20723	0	0	0
T52	0	13	0	0
T53	0	3	0	0
T58	35983	0	0	0
T115	1141	0	0	0
T128	1953	0	0	0
T133	0	3	0	0
T134	0	10	0	0
T135	0	3	0	0
T136	0	18	0	0
T137	0	4	0	0
T138	0	12	0	0
T139	21319	0	0	0
T140	15285	0	0	0
T141	7475	0	0	0
T142	23293	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106955467	1610	0	0
T16	547036	1	0	0
T23	39955	0	0	0
T44	20723	0	0	0
T58	35983	0	0	0
T101	0	14	0	0
T103	0	71	0	0
T106	0	36	0	0
T112	0	50	0	0
T115	1141	0	0	0
T128	1953	0	0	0
T139	21319	0	0	0
T140	15285	0	0	0
T141	7475	0	0	0
T142	23293	0	0	0
T143	0	18	0	0
T144	0	3	0	0
T145	0	19	0	0
T146	0	25	0	0
T147	0	1	0	0