Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1729124	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1949372

1

T2

8228

T3

93

T10

1101

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3334137	1			T2	15875		T3	87		T10	903
values[0x0]	171370	1			T2	174		T3	36		T10	404
values[0x1]	172989	1			T2	186		T3	28		T10	388

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1372744	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2305752

1

T2

9889

T3

105

T10

1219

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12084	1			T2	60		T12	1		T14	7
valid_sources[0x01]	12920	1			T2	61		T14	8		T16	3
valid_sources[0x02]	11748	1			T2	67		T14	4		T16	5
valid_sources[0x03]	12244	1			T2	74		T14	6		T16	1
valid_sources[0x04]	11889	1			T2	47		T11	3		T16	3
valid_sources[0x05]	11505	1			T2	50		T11	8		T14	6
valid_sources[0x06]	11943	1			T2	71		T11	11		T14	9
valid_sources[0x07]	11873	1			T2	87		T14	1		T16	5
valid_sources[0x08]	11711	1			T2	64		T3	6		T11	4
valid_sources[0x09]	12750	1			T2	66		T16	8		T22	5
valid_sources[0x0a]	12082	1			T2	62		T3	3		T11	22
valid_sources[0x0b]	14359	1			T2	66		T14	2		T16	4
valid_sources[0x0c]	12216	1			T2	54		T15	42		T16	4
valid_sources[0x0d]	12492	1			T2	62		T14	2		T16	1
valid_sources[0x0e]	11978	1			T2	67		T11	17		T16	5
valid_sources[0x0f]	12252	1			T2	83		T3	2		T16	1
valid_sources[0x10]	11925	1			T2	47		T11	11		T14	2
valid_sources[0x11]	11920	1			T2	57		T11	22		T14	1
valid_sources[0x12]	11881	1			T2	45		T11	11		T14	9
valid_sources[0x13]	12940	1			T2	53		T14	7		T16	6
valid_sources[0x14]	12664	1			T2	59		T11	1		T14	1
valid_sources[0x15]	11402	1			T2	62		T3	2		T14	5
valid_sources[0x16]	29047	1			T2	55		T11	4		T22	4
valid_sources[0x17]	12269	1			T2	62		T14	2		T16	7
valid_sources[0x18]	12138	1			T2	62		T11	6		T14	2
valid_sources[0x19]	12828	1			T2	51		T14	5		T16	5
valid_sources[0x1a]	11893	1			T2	75		T3	2		T14	1
valid_sources[0x1b]	11583	1			T2	68		T11	9		T16	4
valid_sources[0x1c]	12103	1			T2	73		T11	18		T14	2
valid_sources[0x1d]	12701	1			T2	55		T14	4		T16	1
valid_sources[0x1e]	13003	1			T2	72		T16	1		T22	1
valid_sources[0x1f]	12948	1			T2	61		T11	7		T22	6
valid_sources[0x20]	11825	1			T2	67		T11	1		T14	6
valid_sources[0x21]	13788	1			T2	63		T14	3		T16	3
valid_sources[0x22]	11600	1			T2	49		T11	2		T12	1
valid_sources[0x23]	11961	1			T2	68		T3	6		T16	3
valid_sources[0x24]	11926	1			T2	66		T11	1		T14	4
valid_sources[0x25]	11338	1			T2	71		T11	5		T14	10
valid_sources[0x26]	29757	1			T2	55		T14	5		T16	5
valid_sources[0x27]	13483	1			T2	57		T11	29		T14	2
valid_sources[0x28]	12848	1			T2	48		T16	4		T22	16
valid_sources[0x29]	11959	1			T2	78		T14	4		T16	1
valid_sources[0x2a]	14169	1			T2	75		T11	13		T14	2
valid_sources[0x2b]	29658	1			T2	80		T14	1		T16	1
valid_sources[0x2c]	13370	1			T2	71		T3	2		T14	1
valid_sources[0x2d]	12408	1			T2	65		T11	2		T16	5
valid_sources[0x2e]	11709	1			T2	58		T11	8		T16	1
valid_sources[0x2f]	12222	1			T2	62		T14	3		T16	4
valid_sources[0x30]	15449	1			T2	80		T16	8		T22	14
valid_sources[0x31]	11902	1			T2	65		T14	1		T16	5
valid_sources[0x32]	11893	1			T2	56		T11	8		T14	2
valid_sources[0x33]	13422	1			T2	60		T14	2		T16	7
valid_sources[0x34]	13747	1			T2	58		T14	1		T16	10
valid_sources[0x35]	13998	1			T2	52		T14	5		T16	5
valid_sources[0x36]	12787	1			T2	52		T11	10		T14	3
valid_sources[0x37]	11714	1			T2	58		T16	5		T22	6
valid_sources[0x38]	14413	1			T2	85		T3	3		T11	3
valid_sources[0x39]	12335	1			T2	65		T11	2		T14	1
valid_sources[0x3a]	11731	1			T2	65		T3	4		T11	19
valid_sources[0x3b]	40752	1			T2	70		T11	5		T14	1
valid_sources[0x3c]	11341	1			T2	61		T11	4		T14	3
valid_sources[0x3d]	11979	1			T2	70		T16	2		T22	1
valid_sources[0x3e]	12095	1			T2	44		T3	2		T16	3
valid_sources[0x3f]	13239	1			T2	64		T14	10		T16	5
valid_sources[0x40]	11294	1			T2	53		T3	2		T16	4
valid_sources[0x41]	13195	1			T2	67		T11	5		T14	1
valid_sources[0x42]	17341	1			T2	60		T11	6		T14	2
valid_sources[0x43]	28101	1			T2	62		T14	3		T16	10
valid_sources[0x44]	11630	1			T2	47		T14	3		T16	4
valid_sources[0x45]	13335	1			T2	69		T14	2		T16	7
valid_sources[0x46]	11516	1			T2	58		T11	4		T14	3
valid_sources[0x47]	12215	1			T2	88		T11	13		T22	15
valid_sources[0x48]	11975	1			T2	63		T3	5		T11	12
valid_sources[0x49]	16768	1			T2	60		T11	34		T14	7
valid_sources[0x4a]	11887	1			T2	53		T14	1		T16	4
valid_sources[0x4b]	12249	1			T2	77		T11	25		T14	1
valid_sources[0x4c]	15155	1			T2	62		T10	1695		T11	4
valid_sources[0x4d]	12613	1			T2	68		T12	2		T14	4
valid_sources[0x4e]	12820	1			T2	69		T14	5		T16	4
valid_sources[0x4f]	11913	1			T2	65		T14	3		T16	1
valid_sources[0x50]	21128	1			T2	71		T14	6		T16	1
valid_sources[0x51]	33503	1			T2	63		T14	1		T16	6
valid_sources[0x52]	14022	1			T2	62		T14	7		T16	4
valid_sources[0x53]	12123	1			T2	54		T11	14		T14	2
valid_sources[0x54]	12984	1			T2	54		T11	1		T16	6
valid_sources[0x55]	13166	1			T2	54		T11	7		T16	3
valid_sources[0x56]	12406	1			T2	72		T11	8		T14	3
valid_sources[0x57]	12062	1			T2	75		T14	8		T16	6
valid_sources[0x58]	11994	1			T2	60		T11	37		T22	14
valid_sources[0x59]	12393	1			T2	63		T14	1		T16	3
valid_sources[0x5a]	11893	1			T2	81		T15	68		T16	3
valid_sources[0x5b]	12897	1			T2	64		T3	9		T14	3
valid_sources[0x5c]	13325	1			T2	75		T11	6		T14	3
valid_sources[0x5d]	14139	1			T2	45		T3	1		T11	13
valid_sources[0x5e]	11948	1			T2	85		T14	5		T16	1
valid_sources[0x5f]	13349	1			T2	80		T11	9		T14	5
valid_sources[0x60]	12115	1			T2	61		T11	2		T16	3
valid_sources[0x61]	12410	1			T2	67		T11	5		T14	8
valid_sources[0x62]	12331	1			T2	69		T3	3		T11	6
valid_sources[0x63]	11973	1			T2	72		T3	12		T14	5
valid_sources[0x64]	11762	1			T2	73		T11	23		T14	1
valid_sources[0x65]	12038	1			T2	68		T14	3		T16	4
valid_sources[0x66]	11779	1			T2	77		T14	6		T16	3
valid_sources[0x67]	11718	1			T2	77		T12	3		T14	2
valid_sources[0x68]	11957	1			T2	62		T14	2		T16	4
valid_sources[0x69]	12505	1			T2	64		T11	22		T14	4
valid_sources[0x6a]	12336	1			T2	73		T14	2		T16	9
valid_sources[0x6b]	12063	1			T2	59		T11	1		T14	1
valid_sources[0x6c]	12423	1			T2	66		T11	19		T14	1
valid_sources[0x6d]	11412	1			T2	62		T14	2		T16	6
valid_sources[0x6e]	12040	1			T2	60		T11	7		T14	3
valid_sources[0x6f]	13918	1			T2	57		T13	1929		T14	7
valid_sources[0x70]	11870	1			T2	63		T16	2		T22	12
valid_sources[0x71]	11801	1			T2	58		T11	14		T14	2
valid_sources[0x72]	27758	1			T2	63		T11	10		T14	1
valid_sources[0x73]	11737	1			T2	61		T14	9		T16	6
valid_sources[0x74]	11704	1			T2	41		T3	3		T11	3
valid_sources[0x75]	12958	1			T2	73		T3	6		T14	1
valid_sources[0x76]	12118	1			T2	67		T3	6		T14	7
valid_sources[0x77]	13078	1			T2	50		T14	9		T22	3
valid_sources[0x78]	11508	1			T2	63		T14	1		T16	5
valid_sources[0x79]	12320	1			T2	62		T11	5		T16	3
valid_sources[0x7a]	11936	1			T2	63		T3	3		T11	10
valid_sources[0x7b]	11554	1			T2	53		T11	12		T14	1
valid_sources[0x7c]	15388	1			T2	58		T14	2		T16	9
valid_sources[0x7d]	12443	1			T2	87		T11	3		T14	1
valid_sources[0x7e]	13297	1			T2	71		T11	8		T14	2
valid_sources[0x7f]	11793	1			T2	73		T14	8		T16	1
valid_sources[0x80]	11596	1			T2	66		T3	6		T14	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1652763

1

T2

7910

T3

35

T10

419

values[0x0]

all_enables

biggest_size

148382

1

T2

152

T3

33

T10

344

values[0x1]

all_enables

biggest_size

148227

1

T2

166

T3

25

T10

338