Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	100.00	82.35	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	111348679	13914	0	0
claim_transition_if_regwen_rd_A	111348679	1572	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111348679	13914	0	0
T43	62115	0	0	0
T44	0	16	0	0
T46	0	12	0	0
T57	3255	0	0	0
T83	311551	3	0	0
T86	0	4	0	0
T98	0	6	0	0
T99	0	7	0	0
T127	0	1	0	0
T155	0	9	0	0
T156	0	8	0	0
T157	0	3	0	0
T158	73173	0	0	0
T159	27505	0	0	0
T160	7675	0	0	0
T161	31349	0	0	0
T162	52828	0	0	0
T163	91562	0	0	0
T164	27458	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111348679	1572	0	0
T51	20064	0	0	0
T86	537234	12	0	0
T108	817	0	0	0
T109	32402	0	0	0
T110	45422	0	0	0
T122	0	6	0	0
T153	0	10	0	0
T157	0	16	0	0
T165	0	7	0	0
T166	0	11	0	0
T167	0	3	0	0
T168	0	159	0	0
T169	0	35	0	0
T170	0	13	0	0
T171	39187	0	0	0
T172	38852	0	0	0
T173	169498	0	0	0
T174	17418	0	0	0
T175	897187	0	0	0