Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1686647	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1901867

1

T1

6

T2

55

T3

685

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3249245	1			T1	43		T2	52		T3	525
values[0x0]	169274	1			T1	2		T2	13		T3	252
values[0x1]	169995	1			T1	6		T2	19		T3	268

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1340119	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2248395

1

T1

20

T2

59

T3

769

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10403	1			T3	4		T4	3		T5	498
valid_sources[0x01]	10585	1			T1	1		T3	2		T4	7
valid_sources[0x02]	11181	1			T3	3		T5	707		T17	5
valid_sources[0x03]	12020	1			T1	1		T3	6		T4	12
valid_sources[0x04]	10533	1			T1	1		T3	7		T4	11
valid_sources[0x05]	10588	1			T1	1		T3	2		T4	6
valid_sources[0x06]	17174	1			T1	1		T3	6		T4	8
valid_sources[0x07]	11697	1			T3	4		T4	6		T5	604
valid_sources[0x08]	10663	1			T3	7		T4	4		T5	383
valid_sources[0x09]	10827	1			T3	1		T5	387		T17	5
valid_sources[0x0a]	10722	1			T3	2		T4	7		T5	468
valid_sources[0x0b]	11090	1			T3	4		T4	3		T5	576
valid_sources[0x0c]	10222	1			T3	4		T4	6		T5	474
valid_sources[0x0d]	11907	1			T3	3		T4	7		T5	427
valid_sources[0x0e]	10968	1			T3	2		T4	10		T5	435
valid_sources[0x0f]	32745	1			T3	6		T4	6		T5	498
valid_sources[0x10]	11873	1			T3	2		T4	19		T5	468
valid_sources[0x11]	11016	1			T3	5		T4	3		T5	455
valid_sources[0x12]	10742	1			T3	2		T4	6		T5	532
valid_sources[0x13]	10804	1			T3	3		T4	6		T5	500
valid_sources[0x14]	10390	1			T3	3		T5	430		T17	4
valid_sources[0x15]	11685	1			T3	5		T4	10		T5	479
valid_sources[0x16]	11898	1			T3	3		T4	11		T5	577
valid_sources[0x17]	137260	1			T3	2		T4	1		T5	458
valid_sources[0x18]	10786	1			T3	4		T4	3		T5	398
valid_sources[0x19]	11253	1			T3	7		T4	2		T5	480
valid_sources[0x1a]	10834	1			T3	6		T4	4		T5	603
valid_sources[0x1b]	10872	1			T3	3		T4	6		T5	627
valid_sources[0x1c]	10939	1			T3	4		T4	3		T5	501
valid_sources[0x1d]	10943	1			T1	1		T4	3		T5	451
valid_sources[0x1e]	71234	1			T4	4		T5	527		T13	1
valid_sources[0x1f]	10848	1			T3	1		T4	10		T5	462
valid_sources[0x20]	11308	1			T1	1		T3	3		T4	8
valid_sources[0x21]	11050	1			T3	9		T4	3		T5	393
valid_sources[0x22]	10505	1			T3	4		T5	410		T17	2
valid_sources[0x23]	11121	1			T1	1		T3	1		T5	529
valid_sources[0x24]	10286	1			T3	1		T4	8		T5	372
valid_sources[0x25]	15023	1			T1	1		T4	1		T5	279
valid_sources[0x26]	10345	1			T3	3		T4	1		T5	337
valid_sources[0x27]	10244	1			T3	3		T4	3		T5	463
valid_sources[0x28]	10317	1			T3	1		T4	1		T5	383
valid_sources[0x29]	11144	1			T3	5		T4	8		T5	380
valid_sources[0x2a]	10732	1			T1	1		T3	3		T5	481
valid_sources[0x2b]	22144	1			T3	2		T4	4		T5	540
valid_sources[0x2c]	11555	1			T3	11		T4	3		T5	453
valid_sources[0x2d]	11044	1			T3	1		T4	5		T5	456
valid_sources[0x2e]	16033	1			T3	6		T4	4		T5	459
valid_sources[0x2f]	10816	1			T3	6		T4	4		T5	502
valid_sources[0x30]	10977	1			T3	1		T5	463		T17	6
valid_sources[0x31]	12810	1			T3	7		T4	3		T5	477
valid_sources[0x32]	15476	1			T3	7		T5	592		T13	2
valid_sources[0x33]	10617	1			T3	4		T4	3		T5	396
valid_sources[0x34]	11099	1			T3	5		T4	8		T5	336
valid_sources[0x35]	10411	1			T3	5		T4	16		T5	420
valid_sources[0x36]	11939	1			T3	5		T5	460		T13	2
valid_sources[0x37]	14883	1			T3	2		T5	346		T17	1
valid_sources[0x38]	10913	1			T3	5		T4	5		T5	448
valid_sources[0x39]	10607	1			T3	6		T4	12		T5	469
valid_sources[0x3a]	11331	1			T3	1		T4	8		T5	464
valid_sources[0x3b]	12416	1			T3	5		T5	430		T17	7
valid_sources[0x3c]	10885	1			T1	1		T3	8		T4	1
valid_sources[0x3d]	12599	1			T1	1		T3	3		T4	3
valid_sources[0x3e]	12281	1			T4	1		T5	462		T13	2
valid_sources[0x3f]	10586	1			T3	2		T4	11		T5	353
valid_sources[0x40]	10703	1			T4	5		T5	394		T17	4
valid_sources[0x41]	10745	1			T3	4		T4	12		T5	358
valid_sources[0x42]	12067	1			T1	1		T3	3		T4	7
valid_sources[0x43]	11244	1			T3	2		T4	7		T5	405
valid_sources[0x44]	10713	1			T3	3		T4	3		T5	348
valid_sources[0x45]	12233	1			T3	2		T5	413		T17	3
valid_sources[0x46]	10516	1			T3	5		T4	2		T5	336
valid_sources[0x47]	11779	1			T3	7		T5	490		T13	1
valid_sources[0x48]	15100	1			T3	3		T4	9		T5	425
valid_sources[0x49]	10779	1			T3	7		T4	9		T5	543
valid_sources[0x4a]	10467	1			T1	1		T3	5		T4	2
valid_sources[0x4b]	11771	1			T1	1		T3	3		T4	2
valid_sources[0x4c]	10468	1			T3	5		T4	4		T5	459
valid_sources[0x4d]	17690	1			T1	1		T3	4		T4	15
valid_sources[0x4e]	12882	1			T3	2		T4	2		T5	523
valid_sources[0x4f]	11476	1			T3	3		T5	417		T17	4
valid_sources[0x50]	200878	1			T1	1		T3	7		T4	7
valid_sources[0x51]	11089	1			T3	7		T4	1		T5	346
valid_sources[0x52]	10420	1			T3	2		T4	6		T5	449
valid_sources[0x53]	10702	1			T3	4		T4	3		T5	371
valid_sources[0x54]	10908	1			T3	8		T4	1		T5	473
valid_sources[0x55]	10667	1			T3	4		T4	3		T5	432
valid_sources[0x56]	11562	1			T3	3		T4	4		T5	409
valid_sources[0x57]	10675	1			T3	5		T4	5		T5	470
valid_sources[0x58]	10467	1			T3	3		T4	3		T5	396
valid_sources[0x59]	11033	1			T3	6		T5	472		T17	1
valid_sources[0x5a]	10372	1			T3	4		T4	5		T5	461
valid_sources[0x5b]	12056	1			T3	10		T4	2		T5	313
valid_sources[0x5c]	13425	1			T3	1		T4	5		T5	446
valid_sources[0x5d]	11711	1			T3	6		T4	16		T5	551
valid_sources[0x5e]	10236	1			T3	4		T4	2		T5	378
valid_sources[0x5f]	22334	1			T1	1		T3	1		T4	2
valid_sources[0x60]	10598	1			T3	2		T4	9		T5	345
valid_sources[0x61]	10506	1			T3	5		T4	2		T5	357
valid_sources[0x62]	10081	1			T3	6		T4	2		T5	257
valid_sources[0x63]	11763	1			T3	4		T4	5		T5	343
valid_sources[0x64]	10864	1			T3	5		T4	6		T5	682
valid_sources[0x65]	11842	1			T3	10		T4	1		T5	442
valid_sources[0x66]	11128	1			T3	4		T4	3		T5	351
valid_sources[0x67]	11118	1			T1	1		T3	1		T5	549
valid_sources[0x68]	10887	1			T3	3		T4	9		T5	448
valid_sources[0x69]	10374	1			T3	6		T4	5		T5	324
valid_sources[0x6a]	10539	1			T1	1		T3	3		T4	2
valid_sources[0x6b]	11775	1			T3	3		T4	2		T5	571
valid_sources[0x6c]	10697	1			T3	9		T4	7		T5	523
valid_sources[0x6d]	10554	1			T3	4		T4	1		T5	430
valid_sources[0x6e]	10897	1			T3	6		T5	508		T17	4
valid_sources[0x6f]	10978	1			T3	3		T4	5		T5	515
valid_sources[0x70]	69685	1			T3	8		T4	7		T5	442
valid_sources[0x71]	10215	1			T3	3		T4	2		T5	435
valid_sources[0x72]	13818	1			T3	3		T4	2		T5	585
valid_sources[0x73]	10854	1			T3	7		T4	3		T5	468
valid_sources[0x74]	10270	1			T3	6		T4	4		T5	482
valid_sources[0x75]	10683	1			T3	10		T5	417		T17	3
valid_sources[0x76]	10164	1			T1	1		T3	1		T4	4
valid_sources[0x77]	15296	1			T3	9		T4	11		T5	539
valid_sources[0x78]	12831	1			T3	3		T4	7		T5	494
valid_sources[0x79]	11031	1			T3	6		T5	326		T13	1
valid_sources[0x7a]	13213	1			T3	4		T5	528		T13	3
valid_sources[0x7b]	10799	1			T3	6		T4	8		T5	455
valid_sources[0x7c]	10548	1			T3	4		T4	9		T5	414
valid_sources[0x7d]	10443	1			T3	1		T4	1		T5	350
valid_sources[0x7e]	51518	1			T3	1		T4	13		T5	502
valid_sources[0x7f]	10400	1			T4	2		T5	424		T17	6
valid_sources[0x80]	10959	1			T3	2		T4	9		T5	517

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1609608

1

T2

29

T3

235

T4

234

values[0x0]

all_enables

biggest_size

146596

1

T1

2

T2

11

T3

213

values[0x1]

all_enables

biggest_size

145663

1

T1

4

T2

15

T3

237