Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	111181167	13652	0	0
claim_transition_if_regwen_rd_A	111181167	1627	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111181167	13652	0	0
T5	302680	13	0	0
T6	34775	0	0	0
T11	902	0	0	0
T12	623356	0	0	0
T13	1782	0	0	0
T14	7931	0	0	0
T15	225432	0	0	0
T16	42580	0	0	0
T17	29046	0	0	0
T18	0	9	0	0
T19	0	1	0	0
T20	0	3	0	0
T41	0	11	0	0
T55	1222	0	0	0
T109	0	9	0	0
T150	0	2	0	0
T151	0	2	0	0
T152	0	5	0	0
T153	0	5	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111181167	1627	0	0
T116	11860	83	0	0
T118	13253	2	0	0
T122	8392	7	0	0
T137	10874	56	0	0
T148	5026	6	0	0
T154	8956	406	0	0
T155	4376	58	0	0
T156	3611	8	0	0
T157	2212	7	0	0
T158	1559	1	0	0