Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1360758	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1575431

1

T1

9

T2

1019

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2603878	1			T2	843		T3	4		T4	249
values[0x0]	165916	1			T1	19		T2	387		T3	4
values[0x1]	166395	1			T1	20		T2	349		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1080120	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1856069

1

T1

14

T2

1144

T3

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8225	1			T4	5		T14	1		T15	9
valid_sources[0x01]	8179	1			T4	1		T14	5		T15	7
valid_sources[0x02]	9724	1			T14	11		T15	3		T16	6
valid_sources[0x03]	8545	1			T4	5		T14	5		T16	3
valid_sources[0x04]	20191	1			T4	4		T14	5		T15	1
valid_sources[0x05]	8333	1			T4	3		T14	4		T15	1
valid_sources[0x06]	8227	1			T4	2		T14	1		T15	5
valid_sources[0x07]	8334	1			T4	2		T14	3		T16	9
valid_sources[0x08]	8320	1			T4	8		T15	1		T16	7
valid_sources[0x09]	8670	1			T4	1		T14	1		T15	2
valid_sources[0x0a]	9712	1			T4	2		T14	2		T15	1
valid_sources[0x0b]	10867	1			T4	1		T14	9		T15	4
valid_sources[0x0c]	36405	1			T14	2		T16	4		T20	3
valid_sources[0x0d]	8492	1			T4	3		T14	2		T15	1
valid_sources[0x0e]	8624	1			T4	3		T14	7		T15	6
valid_sources[0x0f]	8288	1			T4	4		T14	4		T15	6
valid_sources[0x10]	15660	1			T4	4		T14	5		T15	2
valid_sources[0x11]	8953	1			T4	3		T14	6		T16	8
valid_sources[0x12]	18015	1			T14	6		T15	5		T16	3
valid_sources[0x13]	8345	1			T1	2		T4	1		T14	6
valid_sources[0x14]	47375	1			T1	1		T4	1		T14	1
valid_sources[0x15]	8367	1			T4	2		T14	9		T15	1
valid_sources[0x16]	8755	1			T4	4		T14	4		T15	2
valid_sources[0x17]	8153	1			T4	2		T14	8		T15	2
valid_sources[0x18]	8133	1			T4	1		T14	5		T15	2
valid_sources[0x19]	8242	1			T4	5		T14	2		T15	3
valid_sources[0x1a]	9683	1			T4	2		T14	2		T15	5
valid_sources[0x1b]	8380	1			T4	2		T14	2		T15	1
valid_sources[0x1c]	8117	1			T1	1		T4	1		T14	5
valid_sources[0x1d]	8309	1			T1	1		T4	2		T15	2
valid_sources[0x1e]	8698	1			T4	1		T14	10		T15	7
valid_sources[0x1f]	27005	1			T4	2		T6	1		T14	3
valid_sources[0x20]	10091	1			T4	1		T14	16		T15	6
valid_sources[0x21]	8300	1			T4	4		T14	4		T15	2
valid_sources[0x22]	7907	1			T4	4		T14	5		T15	2
valid_sources[0x23]	120839	1			T14	2		T15	8		T16	11
valid_sources[0x24]	8449	1			T2	8		T4	3		T14	4
valid_sources[0x25]	8190	1			T4	2		T13	1		T14	4
valid_sources[0x26]	8321	1			T3	2		T4	3		T14	13
valid_sources[0x27]	8133	1			T6	21		T14	7		T15	5
valid_sources[0x28]	9714	1			T4	3		T15	3		T16	8
valid_sources[0x29]	8658	1			T2	113		T4	2		T14	9
valid_sources[0x2a]	8563	1			T4	2		T16	5		T22	5
valid_sources[0x2b]	8100	1			T3	4		T4	5		T14	3
valid_sources[0x2c]	24610	1			T4	1		T14	2		T16	6
valid_sources[0x2d]	8399	1			T4	5		T14	5		T15	2
valid_sources[0x2e]	12405	1			T15	5		T16	7		T20	12
valid_sources[0x2f]	31594	1			T4	2		T14	5		T15	4
valid_sources[0x30]	9090	1			T4	6		T6	1		T14	6
valid_sources[0x31]	8202	1			T4	5		T14	9		T15	5
valid_sources[0x32]	8226	1			T4	3		T14	5		T15	4
valid_sources[0x33]	8180	1			T4	2		T14	10		T15	7
valid_sources[0x34]	28515	1			T2	139		T4	1		T14	4
valid_sources[0x35]	8093	1			T1	1		T4	3		T14	1
valid_sources[0x36]	9939	1			T4	1		T14	8		T15	2
valid_sources[0x37]	8995	1			T2	82		T4	4		T14	2
valid_sources[0x38]	9601	1			T4	1		T14	10		T16	7
valid_sources[0x39]	9363	1			T14	1		T15	1		T16	12
valid_sources[0x3a]	9516	1			T4	8		T14	3		T15	5
valid_sources[0x3b]	8262	1			T4	3		T14	7		T15	2
valid_sources[0x3c]	8223	1			T14	2		T15	10		T16	5
valid_sources[0x3d]	8341	1			T2	55		T4	1		T14	2
valid_sources[0x3e]	8568	1			T1	1		T4	1		T14	4
valid_sources[0x3f]	8965	1			T1	1		T14	4		T15	3
valid_sources[0x40]	8581	1			T4	4		T14	2		T15	3
valid_sources[0x41]	8404	1			T4	6		T14	2		T15	3
valid_sources[0x42]	8183	1			T4	6		T14	5		T15	8
valid_sources[0x43]	8158	1			T4	2		T14	1		T15	4
valid_sources[0x44]	9782	1			T4	4		T14	4		T15	4
valid_sources[0x45]	8506	1			T1	1		T4	1		T14	1
valid_sources[0x46]	12956	1			T4	5		T14	1		T15	4
valid_sources[0x47]	8157	1			T4	3		T14	2		T15	5
valid_sources[0x48]	8189	1			T4	1		T14	1		T15	3
valid_sources[0x49]	8218	1			T4	3		T16	5		T20	4
valid_sources[0x4a]	8255	1			T4	4		T14	9		T15	5
valid_sources[0x4b]	10664	1			T14	6		T15	4		T16	6
valid_sources[0x4c]	17913	1			T4	3		T14	7		T16	4
valid_sources[0x4d]	11268	1			T1	1		T4	3		T14	7
valid_sources[0x4e]	8227	1			T4	2		T6	8		T14	7
valid_sources[0x4f]	9761	1			T4	5		T14	6		T15	1
valid_sources[0x50]	8272	1			T4	3		T14	4		T15	3
valid_sources[0x51]	28121	1			T4	4		T14	1		T15	1
valid_sources[0x52]	8262	1			T4	2		T14	6		T15	3
valid_sources[0x53]	8379	1			T4	1		T14	12		T15	4
valid_sources[0x54]	8382	1			T4	2		T14	4		T15	6
valid_sources[0x55]	8312	1			T4	7		T14	8		T15	1
valid_sources[0x56]	8158	1			T14	10		T15	3		T16	8
valid_sources[0x57]	9445	1			T4	3		T14	2		T15	4
valid_sources[0x58]	8791	1			T4	2		T14	10		T15	2
valid_sources[0x59]	8347	1			T4	3		T14	2		T15	3
valid_sources[0x5a]	8357	1			T4	5		T14	1		T15	2
valid_sources[0x5b]	9841	1			T14	1		T15	3		T16	13
valid_sources[0x5c]	10188	1			T14	7		T15	10		T16	14
valid_sources[0x5d]	8265	1			T4	3		T14	2		T15	1
valid_sources[0x5e]	8372	1			T14	4		T15	1		T16	10
valid_sources[0x5f]	8193	1			T4	1		T14	3		T15	3
valid_sources[0x60]	8329	1			T4	6		T15	2		T16	13
valid_sources[0x61]	8505	1			T2	134		T13	1		T14	7
valid_sources[0x62]	10703	1			T14	2		T15	1		T16	13
valid_sources[0x63]	8094	1			T4	2		T13	3		T14	3
valid_sources[0x64]	8337	1			T4	1		T14	6		T15	3
valid_sources[0x65]	9009	1			T4	3		T14	2		T15	4
valid_sources[0x66]	10704	1			T4	1		T14	2		T16	8
valid_sources[0x67]	15900	1			T4	4		T14	2		T15	2
valid_sources[0x68]	8402	1			T4	2		T14	2		T15	3
valid_sources[0x69]	9709	1			T4	4		T14	2		T15	6
valid_sources[0x6a]	10114	1			T1	2		T4	3		T14	3
valid_sources[0x6b]	10249	1			T2	27		T4	4		T14	2
valid_sources[0x6c]	8281	1			T4	4		T15	8		T16	6
valid_sources[0x6d]	9877	1			T1	1		T4	1		T14	6
valid_sources[0x6e]	35649	1			T2	109		T4	5		T14	7
valid_sources[0x6f]	79261	1			T1	1		T4	3		T14	7
valid_sources[0x70]	8050	1			T4	1		T14	4		T15	2
valid_sources[0x71]	9755	1			T4	3		T14	3		T15	3
valid_sources[0x72]	8397	1			T1	1		T4	6		T14	8
valid_sources[0x73]	9710	1			T4	5		T14	3		T15	6
valid_sources[0x74]	8513	1			T4	3		T14	6		T15	7
valid_sources[0x75]	10163	1			T4	3		T14	3		T15	2
valid_sources[0x76]	8317	1			T4	4		T14	16		T15	3
valid_sources[0x77]	11507	1			T15	2		T16	11		T22	1
valid_sources[0x78]	8415	1			T4	7		T6	6		T14	3
valid_sources[0x79]	8038	1			T1	2		T4	2		T14	4
valid_sources[0x7a]	8169	1			T4	2		T13	1		T14	6
valid_sources[0x7b]	17349	1			T4	5		T14	1		T16	17
valid_sources[0x7c]	9709	1			T4	3		T14	5		T15	1
valid_sources[0x7d]	9765	1			T1	1		T2	294		T4	5
valid_sources[0x7e]	8146	1			T1	2		T4	4		T14	6
valid_sources[0x7f]	10062	1			T2	188		T4	1		T14	2
valid_sources[0x80]	8390	1			T14	4		T15	10		T16	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1288965

1

T2

389

T4

118

T6

27

values[0x0]

all_enables

biggest_size

143914

1

T1

7

T2

325

T3

3

values[0x1]

all_enables

biggest_size

142552

1

T1

2

T2

305

T3

3