Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	92867341	13339	0	0
claim_transition_if_regwen_rd_A	92867341	1363	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92867341	13339	0	0
T7	152790	6	0	0
T8	123799	0	0	0
T18	73711	0	0	0
T23	201520	0	0	0
T24	48592	0	0	0
T25	157234	0	0	0
T26	220035	12	0	0
T27	146542	6	0	0
T59	0	5	0	0
T61	10654	0	0	0
T85	0	9	0	0
T87	1467	0	0	0
T95	0	2	0	0
T97	0	4	0	0
T99	0	8	0	0
T138	0	2	0	0
T139	0	2	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92867341	1363	0	0
T100	25462	0	0	0
T104	0	48	0	0
T105	0	13	0	0
T107	0	14	0	0
T109	0	37	0	0
T139	371133	3	0	0
T140	0	8	0	0
T141	0	8	0	0
T142	0	9	0	0
T143	0	8	0	0
T144	0	3	0	0
T145	1204	0	0	0
T146	1248	0	0	0
T147	46090	0	0	0
T148	9876	0	0	0
T149	7072	0	0	0
T150	15722	0	0	0
T151	149359	0	0	0
T152	30803	0	0	0