Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1657488	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1875699

1

T2

42

T3

30106

T8

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3194217	1			T2	41		T3	56387		T8	2
values[0x0]	169042	1			T2	9		T3	1227		T9	2
values[0x1]	169928	1			T2	15		T3	1259		T8	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1316603	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2216584

1

T2

48

T3

36068

T8

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11968	1			T3	264		T10	2		T12	9
valid_sources[0x01]	10182	1			T3	260		T10	1		T11	15
valid_sources[0x02]	11204	1			T3	246		T11	2		T12	12
valid_sources[0x03]	9965	1			T2	1		T3	210		T10	3
valid_sources[0x04]	9937	1			T3	195		T10	1		T11	5
valid_sources[0x05]	10003	1			T3	217		T10	2		T11	3
valid_sources[0x06]	12684	1			T3	225		T10	1		T11	3
valid_sources[0x07]	10298	1			T3	218		T10	2		T11	6
valid_sources[0x08]	12387	1			T3	219		T11	1		T12	13
valid_sources[0x09]	10774	1			T2	1		T3	240		T11	3
valid_sources[0x0a]	15038	1			T3	204		T11	18		T12	6
valid_sources[0x0b]	11102	1			T3	215		T11	2		T12	11
valid_sources[0x0c]	10076	1			T2	1		T3	211		T10	1
valid_sources[0x0d]	10398	1			T3	228		T10	1		T11	10
valid_sources[0x0e]	11433	1			T2	1		T3	215		T11	1
valid_sources[0x0f]	16012	1			T3	203		T10	1		T11	5
valid_sources[0x10]	10344	1			T3	254		T10	3		T11	10
valid_sources[0x11]	10062	1			T3	241		T10	3		T11	2
valid_sources[0x12]	10420	1			T3	263		T10	3		T11	7
valid_sources[0x13]	10525	1			T3	253		T12	4		T13	2
valid_sources[0x14]	11790	1			T3	235		T10	1		T12	5
valid_sources[0x15]	10971	1			T3	236		T10	3		T12	7
valid_sources[0x16]	10147	1			T3	214		T11	9		T12	8
valid_sources[0x17]	10233	1			T3	252		T10	1		T11	3
valid_sources[0x18]	10018	1			T3	241		T10	3		T11	7
valid_sources[0x19]	10100	1			T3	212		T10	4		T12	6
valid_sources[0x1a]	10122	1			T2	1		T3	231		T11	2
valid_sources[0x1b]	62434	1			T3	237		T10	2		T12	3
valid_sources[0x1c]	12300	1			T3	209		T10	3		T11	2
valid_sources[0x1d]	11353	1			T3	219		T11	5		T12	6
valid_sources[0x1e]	17318	1			T3	226		T10	2		T11	3
valid_sources[0x1f]	13376	1			T2	1		T3	214		T13	2
valid_sources[0x20]	9712	1			T3	214		T10	2		T11	4
valid_sources[0x21]	9883	1			T3	262		T10	1		T11	13
valid_sources[0x22]	10471	1			T3	221		T11	1		T12	10
valid_sources[0x23]	11177	1			T3	211		T10	1		T11	14
valid_sources[0x24]	9781	1			T3	249		T10	2		T11	2
valid_sources[0x25]	65305	1			T3	216		T11	8		T12	7
valid_sources[0x26]	10261	1			T3	208		T11	17		T12	5
valid_sources[0x27]	15521	1			T2	1		T3	228		T11	8
valid_sources[0x28]	14047	1			T3	265		T11	6		T12	8
valid_sources[0x29]	10110	1			T3	236		T10	1		T11	2
valid_sources[0x2a]	12688	1			T3	231		T10	1		T11	3
valid_sources[0x2b]	10588	1			T3	217		T10	1		T11	5
valid_sources[0x2c]	10164	1			T3	211		T10	6		T12	7
valid_sources[0x2d]	10298	1			T2	1		T3	220		T10	2
valid_sources[0x2e]	10158	1			T2	1		T3	219		T12	4
valid_sources[0x2f]	9870	1			T3	244		T10	1		T12	11
valid_sources[0x30]	10061	1			T3	237		T12	9		T16	8
valid_sources[0x31]	10401	1			T2	1		T3	227		T11	8
valid_sources[0x32]	10224	1			T2	1		T3	241		T11	4
valid_sources[0x33]	10328	1			T3	223		T10	3		T11	8
valid_sources[0x34]	11214	1			T2	1		T3	221		T10	1
valid_sources[0x35]	10336	1			T3	237		T10	1		T11	3
valid_sources[0x36]	10620	1			T3	243		T10	1		T11	3
valid_sources[0x37]	12613	1			T2	2		T3	243		T10	1
valid_sources[0x38]	12408	1			T3	251		T10	1		T11	1
valid_sources[0x39]	10201	1			T3	246		T10	1		T11	6
valid_sources[0x3a]	41998	1			T3	211		T11	1		T12	8
valid_sources[0x3b]	12054	1			T2	1		T3	211		T10	2
valid_sources[0x3c]	11242	1			T3	241		T10	2		T11	8
valid_sources[0x3d]	11805	1			T3	225		T10	1		T12	10
valid_sources[0x3e]	11372	1			T3	212		T10	1		T11	7
valid_sources[0x3f]	10196	1			T3	252		T12	3		T13	2
valid_sources[0x40]	10661	1			T3	264		T10	1		T12	6
valid_sources[0x41]	12086	1			T3	242		T10	1		T11	1
valid_sources[0x42]	10533	1			T2	1		T3	224		T10	3
valid_sources[0x43]	19596	1			T2	1		T3	226		T11	4
valid_sources[0x44]	10090	1			T3	219		T10	1		T11	6
valid_sources[0x45]	10494	1			T3	207		T10	2		T11	6
valid_sources[0x46]	10207	1			T2	1		T3	235		T10	2
valid_sources[0x47]	15630	1			T3	227		T11	7		T12	1
valid_sources[0x48]	11142	1			T3	223		T11	8		T12	4
valid_sources[0x49]	9999	1			T3	202		T10	4		T11	5
valid_sources[0x4a]	10788	1			T3	219		T9	55		T10	5
valid_sources[0x4b]	10670	1			T3	242		T11	7		T12	4
valid_sources[0x4c]	14325	1			T3	211		T10	1		T11	1
valid_sources[0x4d]	10633	1			T2	1		T3	263		T11	4
valid_sources[0x4e]	10200	1			T3	237		T10	1		T11	12
valid_sources[0x4f]	10389	1			T3	248		T11	7		T12	6
valid_sources[0x50]	14550	1			T3	238		T10	1		T12	3
valid_sources[0x51]	10174	1			T3	217		T10	2		T11	1
valid_sources[0x52]	10589	1			T3	279		T10	1		T11	3
valid_sources[0x53]	10393	1			T3	197		T10	2		T11	1
valid_sources[0x54]	10350	1			T2	1		T3	257		T11	3
valid_sources[0x55]	12835	1			T3	218		T10	2		T11	8
valid_sources[0x56]	10114	1			T3	191		T10	1		T11	3
valid_sources[0x57]	9889	1			T3	221		T10	1		T11	6
valid_sources[0x58]	10307	1			T3	252		T10	3		T12	2
valid_sources[0x59]	9928	1			T3	248		T11	3		T12	6
valid_sources[0x5a]	10271	1			T3	193		T12	9		T13	3
valid_sources[0x5b]	13377	1			T3	203		T10	4		T12	6
valid_sources[0x5c]	12301	1			T3	202		T12	9		T16	4
valid_sources[0x5d]	9845	1			T2	1		T3	241		T10	4
valid_sources[0x5e]	9701	1			T2	1		T3	276		T11	4
valid_sources[0x5f]	10164	1			T3	246		T10	6		T11	8
valid_sources[0x60]	10676	1			T3	239		T10	1		T12	5
valid_sources[0x61]	10152	1			T3	215		T10	1		T11	6
valid_sources[0x62]	9962	1			T3	209		T11	9		T12	5
valid_sources[0x63]	10608	1			T3	225		T11	9		T12	6
valid_sources[0x64]	10368	1			T3	235		T10	2		T11	1
valid_sources[0x65]	10781	1			T3	226		T10	2		T11	12
valid_sources[0x66]	26540	1			T3	244		T12	5		T13	4
valid_sources[0x67]	10536	1			T3	219		T10	1		T11	2
valid_sources[0x68]	9915	1			T2	1		T3	230		T10	1
valid_sources[0x69]	10194	1			T3	232		T10	2		T11	3
valid_sources[0x6a]	12215	1			T2	1		T3	244		T10	3
valid_sources[0x6b]	10298	1			T3	205		T10	2		T11	3
valid_sources[0x6c]	9932	1			T3	232		T10	1		T11	5
valid_sources[0x6d]	9818	1			T3	238		T10	1		T11	2
valid_sources[0x6e]	11157	1			T3	208		T11	1		T12	7
valid_sources[0x6f]	10186	1			T3	217		T10	3		T12	5
valid_sources[0x70]	10689	1			T2	1		T3	225		T11	8
valid_sources[0x71]	61024	1			T3	228		T11	4		T12	4
valid_sources[0x72]	10169	1			T3	231		T10	1		T11	1
valid_sources[0x73]	21393	1			T3	230		T10	2		T11	3
valid_sources[0x74]	10091	1			T3	244		T11	2		T12	7
valid_sources[0x75]	10130	1			T2	1		T3	254		T10	5
valid_sources[0x76]	16989	1			T3	240		T11	5		T12	3
valid_sources[0x77]	10537	1			T3	230		T11	5		T12	6
valid_sources[0x78]	10093	1			T3	236		T10	2		T11	1
valid_sources[0x79]	9760	1			T3	211		T10	1		T11	3
valid_sources[0x7a]	12232	1			T3	243		T10	4		T12	6
valid_sources[0x7b]	11301	1			T3	186		T11	1		T12	7
valid_sources[0x7c]	9900	1			T3	223		T11	3		T12	7
valid_sources[0x7d]	10336	1			T3	223		T10	1		T12	9
valid_sources[0x7e]	45703	1			T2	1		T3	233		T10	2
valid_sources[0x7f]	9914	1			T3	188		T10	2		T12	7
valid_sources[0x80]	11442	1			T3	211		T10	2		T11	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1584145

1

T2

21

T3

27943

T8

1

values[0x0]

all_enables

biggest_size

146303

1

T2

7

T3

1072

T9

1

values[0x1]

all_enables

biggest_size

145251

1

T2

14

T3

1091

T9

5