SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 91.67 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_tb.dut.u_otp_lc_data_i_rma_token_valid_if | 83.33 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_otp_lc_data_i_secrets_valid_if | 83.33 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_otp_lc_data_i_test_tokens_valid_if | 83.33 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_clk_byp_ack_i_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if.gen_connect_lc_tx_items[0].lc_tx_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if.gen_connect_lc_tx_items[1].lc_tx_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
false | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 366 | 1 | T36 | 9 | T51 | 14 | T52 | 7 | ||||
others[1] | 324 | 1 | T36 | 6 | T51 | 8 | T52 | 8 | ||||
others[2] | 326 | 1 | T36 | 2 | T51 | 6 | T52 | 10 | ||||
others[3] | 507 | 1 | T51 | 19 | T52 | 9 | T221 | 6 | ||||
true | 54409 | 1 | T1 | 8 | T2 | 4 | T3 | 613 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
true | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 300 | 1 | T36 | 4 | T51 | 11 | T52 | 2 | ||||
others[1] | 318 | 1 | T36 | 14 | T51 | 12 | T52 | 2 | ||||
others[2] | 372 | 1 | T36 | 6 | T51 | 11 | T52 | 4 | ||||
others[3] | 501 | 1 | T36 | 8 | T51 | 10 | T52 | 12 | ||||
false | 54389 | 1 | T1 | 8 | T2 | 4 | T3 | 613 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
false | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 274 | 1 | T51 | 4 | T52 | 6 | T221 | 2 | ||||
others[1] | 314 | 1 | T36 | 4 | T51 | 2 | T221 | 6 | ||||
others[2] | 299 | 1 | T36 | 10 | T51 | 2 | T52 | 2 | ||||
others[3] | 611 | 1 | T36 | 8 | T51 | 6 | T52 | 12 | ||||
true | 54400 | 1 | T1 | 8 | T2 | 4 | T3 | 613 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 143 | 1 | T51 | 3 | T52 | 2 | T221 | 1 | ||||
others[1] | 166 | 1 | T36 | 5 | T51 | 3 | T52 | 1 | ||||
others[2] | 180 | 1 | T36 | 4 | T51 | 2 | T221 | 1 | ||||
others[3] | 256 | 1 | T36 | 4 | T51 | 6 | T52 | 4 | ||||
false | 828387 | 1 | T1 | 11 | T2 | 4 | T3 | 1245 | ||||
true | 773107 | 1 | T1 | 3 | T3 | 632 | T4 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 155 | 1 | T36 | 4 | T51 | 6 | T52 | 3 | ||||
others[1] | 183 | 1 | T36 | 9 | T51 | 9 | T52 | 4 | ||||
others[2] | 159 | 1 | T36 | 2 | T51 | 2 | T52 | 3 | ||||
others[3] | 304 | 1 | T36 | 5 | T51 | 4 | T52 | 7 | ||||
false | 3202778 | 1 | T1 | 9 | T2 | 4 | T3 | 40182 | ||||
true | 3147566 | 1 | T1 | 1 | T3 | 39569 | T4 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 155 | 1 | T36 | 4 | T51 | 6 | T52 | 3 | ||||
others[1] | 183 | 1 | T36 | 9 | T51 | 9 | T52 | 4 | ||||
others[2] | 159 | 1 | T36 | 2 | T51 | 2 | T52 | 3 | ||||
others[3] | 304 | 1 | T36 | 5 | T51 | 4 | T52 | 7 | ||||
false | 3202778 | 1 | T1 | 9 | T2 | 4 | T3 | 40182 | ||||
true | 3147566 | 1 | T1 | 1 | T3 | 39569 | T4 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |