Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	94645516	14283	0	0
claim_transition_if_regwen_rd_A	94645516	852	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94645516	14283	0	0
T3	189161	3	0	0
T4	24266	0	0	0
T8	1217	0	0	0
T9	1253	0	0	0
T10	6045	0	0	0
T11	28587	0	0	0
T12	27166	0	0	0
T13	7099	0	0	0
T14	50228	0	0	0
T15	111155	7	0	0
T38	0	3	0	0
T91	0	15	0	0
T131	0	2	0	0
T132	0	10	0	0
T133	0	4	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94645516	852	0	0
T44	11257	0	0	0
T92	0	9	0	0
T93	0	12	0	0
T98	0	15	0	0
T100	0	23	0	0
T137	371370	12	0	0
T138	0	6	0	0
T139	0	8	0	0
T140	0	3	0	0
T141	0	2	0	0
T142	0	23	0	0
T143	183753	0	0	0
T144	15968	0	0	0
T145	17555	0	0	0
T146	1368	0	0	0
T147	18146	0	0	0
T148	187131	0	0	0
T149	316930	0	0	0
T150	22558	0	0	0