Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1366214	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1583179

1

T1

1091

T2

290

T3

180

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2608489	1			T1	1258		T2	310		T3	136
values[0x0]	170278	1			T1	302		T2	93		T3	64
values[0x1]	170626	1			T1	266		T2	91		T3	80

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1084231	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1865162

1

T1

1243

T2

336

T3

202

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7162	1			T1	10		T11	4		T28	4
valid_sources[0x01]	7056	1			T1	10		T28	9		T16	7
valid_sources[0x02]	27840	1			T1	8		T11	6		T16	8
valid_sources[0x03]	9680	1			T1	6		T11	4		T16	8
valid_sources[0x04]	7477	1			T1	2		T11	3		T16	2
valid_sources[0x05]	9204	1			T1	10		T28	2		T16	7
valid_sources[0x06]	18276	1			T1	7		T28	20		T16	5
valid_sources[0x07]	10141	1			T1	8		T11	2		T16	4
valid_sources[0x08]	7117	1			T1	6		T11	4		T16	4
valid_sources[0x09]	7505	1			T1	5		T11	2		T16	6
valid_sources[0x0a]	7157	1			T1	9		T11	4		T16	3
valid_sources[0x0b]	7151	1			T1	6		T11	2		T16	5
valid_sources[0x0c]	7466	1			T1	8		T28	4		T16	2
valid_sources[0x0d]	7790	1			T1	10		T28	4		T16	5
valid_sources[0x0e]	6885	1			T1	7		T11	7		T28	1
valid_sources[0x0f]	182306	1			T1	4		T11	5		T16	3
valid_sources[0x10]	7144	1			T1	10		T11	4		T16	4
valid_sources[0x11]	10181	1			T1	6		T11	1		T28	7
valid_sources[0x12]	7374	1			T1	5		T11	2		T28	9
valid_sources[0x13]	7266	1			T1	3		T28	1		T16	9
valid_sources[0x14]	7778	1			T1	6		T22	9		T17	8
valid_sources[0x15]	7217	1			T1	8		T11	3		T28	5
valid_sources[0x16]	7239	1			T1	11		T11	4		T28	3
valid_sources[0x17]	6901	1			T1	6		T11	2		T16	10
valid_sources[0x18]	8818	1			T1	7		T11	2		T28	1
valid_sources[0x19]	7396	1			T1	8		T11	3		T28	1
valid_sources[0x1a]	7109	1			T1	13		T11	2		T28	1
valid_sources[0x1b]	7152	1			T1	8		T11	3		T12	1
valid_sources[0x1c]	8817	1			T1	2		T11	2		T28	1
valid_sources[0x1d]	8342	1			T1	7		T11	4		T28	8
valid_sources[0x1e]	7361	1			T1	7		T11	2		T28	1
valid_sources[0x1f]	7251	1			T1	10		T11	2		T28	15
valid_sources[0x20]	8797	1			T1	9		T11	4		T16	12
valid_sources[0x21]	35775	1			T1	13		T16	4		T17	6
valid_sources[0x22]	7653	1			T1	10		T12	3		T28	2
valid_sources[0x23]	7133	1			T1	19		T11	1		T28	2
valid_sources[0x24]	7225	1			T1	3		T11	1		T16	6
valid_sources[0x25]	6905	1			T1	9		T11	1		T28	11
valid_sources[0x26]	8730	1			T1	11		T11	3		T28	9
valid_sources[0x27]	11326	1			T1	7		T3	280		T16	3
valid_sources[0x28]	6949	1			T1	6		T11	2		T16	3
valid_sources[0x29]	8117	1			T1	6		T11	3		T28	16
valid_sources[0x2a]	7010	1			T1	1		T11	2		T16	5
valid_sources[0x2b]	9652	1			T1	14		T11	3		T28	7
valid_sources[0x2c]	7278	1			T1	5		T11	6		T28	1
valid_sources[0x2d]	11050	1			T1	13		T11	1		T28	5
valid_sources[0x2e]	7113	1			T1	13		T11	3		T16	3
valid_sources[0x2f]	8304	1			T1	9		T11	2		T28	5
valid_sources[0x30]	9088	1			T1	5		T25	1366		T16	6
valid_sources[0x31]	46303	1			T1	6		T11	2		T28	3
valid_sources[0x32]	7742	1			T1	5		T11	3		T28	10
valid_sources[0x33]	8608	1			T1	4		T11	4		T28	4
valid_sources[0x34]	8222	1			T1	3		T11	2		T28	6
valid_sources[0x35]	12788	1			T1	5		T11	1		T16	6
valid_sources[0x36]	8252	1			T1	5		T11	3		T16	1
valid_sources[0x37]	6973	1			T1	10		T11	4		T16	7
valid_sources[0x38]	6905	1			T1	6		T11	5		T28	6
valid_sources[0x39]	7125	1			T1	10		T11	1		T28	1
valid_sources[0x3a]	7072	1			T1	6		T11	4		T28	1
valid_sources[0x3b]	7464	1			T1	9		T11	3		T28	18
valid_sources[0x3c]	7475	1			T1	6		T11	2		T27	1
valid_sources[0x3d]	7423	1			T1	6		T11	1		T16	10
valid_sources[0x3e]	7227	1			T1	13		T11	5		T28	5
valid_sources[0x3f]	12438	1			T1	7		T11	2		T28	1
valid_sources[0x40]	7388	1			T1	10		T28	8		T16	4
valid_sources[0x41]	7542	1			T1	9		T11	2		T28	4
valid_sources[0x42]	34758	1			T1	3		T16	7		T8	1
valid_sources[0x43]	7473	1			T1	4		T11	2		T16	6
valid_sources[0x44]	8141	1			T1	7		T16	2		T17	4
valid_sources[0x45]	11195	1			T1	5		T11	4		T16	12
valid_sources[0x46]	14619	1			T1	2		T11	1		T28	12
valid_sources[0x47]	8056	1			T1	4		T11	3		T28	4
valid_sources[0x48]	7343	1			T1	3		T11	2		T16	7
valid_sources[0x49]	7143	1			T1	14		T11	2		T16	2
valid_sources[0x4a]	50702	1			T1	2		T11	1		T16	3
valid_sources[0x4b]	8268	1			T1	6		T16	4		T8	2
valid_sources[0x4c]	7606	1			T1	2		T11	1		T28	2
valid_sources[0x4d]	7069	1			T1	8		T28	5		T16	9
valid_sources[0x4e]	7550	1			T1	5		T28	17		T16	1
valid_sources[0x4f]	7568	1			T1	5		T11	1		T16	1
valid_sources[0x50]	18136	1			T1	7		T11	5		T28	1
valid_sources[0x51]	7237	1			T1	6		T11	2		T28	11
valid_sources[0x52]	7478	1			T1	10		T16	6		T22	7
valid_sources[0x53]	7449	1			T1	7		T11	6		T16	9
valid_sources[0x54]	8408	1			T1	11		T8	1		T17	3
valid_sources[0x55]	7328	1			T1	6		T11	3		T28	8
valid_sources[0x56]	50383	1			T1	6		T28	9		T16	6
valid_sources[0x57]	7302	1			T1	14		T11	1		T16	4
valid_sources[0x58]	15167	1			T1	4		T11	1		T16	9
valid_sources[0x59]	10633	1			T1	4		T11	7		T16	5
valid_sources[0x5a]	8510	1			T1	5		T11	1		T16	3
valid_sources[0x5b]	7601	1			T1	4		T11	9		T28	2
valid_sources[0x5c]	7410	1			T1	10		T11	1		T28	6
valid_sources[0x5d]	18560	1			T1	7		T11	1		T16	1
valid_sources[0x5e]	18354	1			T1	15		T28	10		T16	5
valid_sources[0x5f]	7049	1			T1	12		T11	4		T28	2
valid_sources[0x60]	7224	1			T1	4		T28	1		T16	4
valid_sources[0x61]	7158	1			T1	5		T28	15		T16	2
valid_sources[0x62]	7173	1			T1	4		T11	2		T8	1
valid_sources[0x63]	8574	1			T1	13		T11	4		T28	12
valid_sources[0x64]	7283	1			T1	10		T11	3		T28	19
valid_sources[0x65]	23133	1			T1	3		T11	2		T16	3
valid_sources[0x66]	7307	1			T1	3		T28	20		T16	5
valid_sources[0x67]	7025	1			T1	9		T11	3		T16	7
valid_sources[0x68]	11168	1			T1	5		T11	1		T16	5
valid_sources[0x69]	7417	1			T1	11		T11	2		T16	3
valid_sources[0x6a]	7212	1			T1	4		T17	8		T40	14
valid_sources[0x6b]	9399	1			T1	7		T11	3		T16	7
valid_sources[0x6c]	7452	1			T1	6		T11	1		T16	4
valid_sources[0x6d]	44635	1			T1	7		T11	1		T28	6
valid_sources[0x6e]	27252	1			T1	4		T11	1		T16	10
valid_sources[0x6f]	8881	1			T1	3		T11	2		T28	6
valid_sources[0x70]	7285	1			T1	1		T11	4		T16	5
valid_sources[0x71]	7115	1			T1	7		T11	3		T28	2
valid_sources[0x72]	7002	1			T1	6		T11	3		T28	3
valid_sources[0x73]	7477	1			T1	10		T11	4		T28	1
valid_sources[0x74]	7329	1			T1	6		T11	4		T16	8
valid_sources[0x75]	7302	1			T1	8		T11	3		T28	4
valid_sources[0x76]	8566	1			T1	10		T11	1		T28	11
valid_sources[0x77]	9805	1			T1	6		T11	5		T28	1
valid_sources[0x78]	7429	1			T1	13		T11	1		T28	10
valid_sources[0x79]	16973	1			T1	13		T11	1		T28	2
valid_sources[0x7a]	7358	1			T1	12		T11	2		T28	2
valid_sources[0x7b]	10822	1			T1	7		T16	4		T17	6
valid_sources[0x7c]	8129	1			T1	8		T11	2		T28	3
valid_sources[0x7d]	34970	1			T1	5		T11	1		T12	1
valid_sources[0x7e]	8186	1			T1	8		T11	1		T28	3
valid_sources[0x7f]	7193	1			T1	10		T11	2		T16	8
valid_sources[0x80]	7417	1			T1	4		T11	4		T28	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1289528

1

T1

596

T2

131

T3

55

values[0x0]

all_enables

biggest_size

147702

1

T1

267

T2

81

T3

55

values[0x1]

all_enables

biggest_size

145949

1

T1

228

T2

78

T3

70