Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	105744085	16725	0	0
claim_transition_if_regwen_rd_A	105744085	1105	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105744085	16725	0	0
T24	298513	1	0	0
T46	29125	0	0	0
T53	22339	0	0	0
T68	0	7	0	0
T69	32844	0	0	0
T90	11685	0	0	0
T91	115834	0	0	0
T92	0	2	0	0
T105	920	0	0	0
T106	43303	0	0	0
T107	83788	0	0	0
T109	0	1	0	0
T110	0	3	0	0
T148	0	2	0	0
T149	0	1	0	0
T150	0	10	0	0
T151	0	1	0	0
T152	0	15	0	0
T153	5928	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105744085	1105	0	0
T24	298513	4	0	0
T46	29125	0	0	0
T53	22339	0	0	0
T69	32844	0	0	0
T90	11685	0	0	0
T91	115834	0	0	0
T105	920	0	0	0
T106	43303	0	0	0
T107	83788	0	0	0
T109	0	2	0	0
T113	0	34	0	0
T149	0	5	0	0
T151	0	7	0	0
T153	5928	0	0	0
T154	0	8	0	0
T155	0	10	0	0
T156	0	1	0	0
T157	0	12	0	0
T158	0	5	0	0