Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1711936	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1927958

1

T1

161

T2

406

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3296101	1			T1	111		T2	477		T10	640
values[0x0]	171305	1			T1	62		T2	104		T3	18
values[0x1]	172488	1			T1	66		T2	80		T3	26

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1359153	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2280741

1

T1

178

T2

454

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12560	1			T2	4		T11	2		T5	525
valid_sources[0x01]	11568	1			T2	3		T10	2		T11	1
valid_sources[0x02]	11326	1			T2	1		T10	9		T11	8
valid_sources[0x03]	10860	1			T10	2		T11	6		T5	493
valid_sources[0x04]	11237	1			T2	4		T10	2		T11	9
valid_sources[0x05]	11664	1			T2	1		T10	3		T11	1
valid_sources[0x06]	10951	1			T2	1		T10	2		T11	12
valid_sources[0x07]	11435	1			T2	3		T10	6		T11	2
valid_sources[0x08]	11416	1			T2	12		T10	4		T5	481
valid_sources[0x09]	11281	1			T2	1		T10	2		T11	8
valid_sources[0x0a]	10976	1			T2	4		T11	2		T5	465
valid_sources[0x0b]	11523	1			T2	3		T10	8		T11	9
valid_sources[0x0c]	11868	1			T2	1		T10	7		T11	1
valid_sources[0x0d]	14216	1			T2	2		T11	1		T5	485
valid_sources[0x0e]	58314	1			T2	5		T10	2		T5	495
valid_sources[0x0f]	11341	1			T10	1		T11	4		T5	530
valid_sources[0x10]	11075	1			T2	5		T10	6		T11	2
valid_sources[0x11]	11555	1			T2	2		T10	1		T11	7
valid_sources[0x12]	11681	1			T2	9		T10	6		T11	5
valid_sources[0x13]	12344	1			T11	2		T5	488		T13	7
valid_sources[0x14]	19700	1			T2	4		T10	1		T11	4
valid_sources[0x15]	12029	1			T10	7		T11	2		T5	431
valid_sources[0x16]	11476	1			T10	2		T11	9		T12	3
valid_sources[0x17]	14276	1			T2	6		T10	6		T11	6
valid_sources[0x18]	11915	1			T2	1		T10	3		T11	1
valid_sources[0x19]	11097	1			T2	1		T10	6		T11	6
valid_sources[0x1a]	13378	1			T2	6		T11	2		T5	482
valid_sources[0x1b]	12588	1			T2	3		T11	4		T5	520
valid_sources[0x1c]	10981	1			T2	3		T10	11		T11	1
valid_sources[0x1d]	11023	1			T10	6		T11	12		T5	490
valid_sources[0x1e]	16606	1			T2	2		T10	2		T11	7
valid_sources[0x1f]	15541	1			T2	2		T10	3		T11	5
valid_sources[0x20]	11481	1			T10	4		T11	6		T5	500
valid_sources[0x21]	62081	1			T2	7		T10	4		T11	6
valid_sources[0x22]	11417	1			T2	4		T10	2		T11	3
valid_sources[0x23]	11081	1			T2	3		T10	7		T11	3
valid_sources[0x24]	12217	1			T2	6		T10	2		T11	4
valid_sources[0x25]	11964	1			T2	1		T10	3		T11	5
valid_sources[0x26]	11904	1			T2	6		T5	483		T13	3
valid_sources[0x27]	11534	1			T2	5		T10	7		T5	547
valid_sources[0x28]	13242	1			T2	1		T10	1		T11	11
valid_sources[0x29]	13576	1			T2	1		T5	495		T13	6
valid_sources[0x2a]	11679	1			T2	5		T10	1		T11	4
valid_sources[0x2b]	13234	1			T2	3		T10	8		T11	1
valid_sources[0x2c]	70058	1			T2	1		T10	9		T11	20
valid_sources[0x2d]	12128	1			T2	5		T10	5		T11	3
valid_sources[0x2e]	11529	1			T2	7		T10	2		T11	4
valid_sources[0x2f]	11913	1			T2	3		T10	12		T5	463
valid_sources[0x30]	12394	1			T2	2		T10	1		T11	6
valid_sources[0x31]	15236	1			T10	2		T5	479		T13	8
valid_sources[0x32]	11222	1			T2	2		T10	5		T11	2
valid_sources[0x33]	10832	1			T2	1		T10	3		T5	488
valid_sources[0x34]	11076	1			T2	4		T10	5		T11	5
valid_sources[0x35]	13334	1			T2	3		T10	2		T11	3
valid_sources[0x36]	11856	1			T2	2		T10	4		T11	8
valid_sources[0x37]	11829	1			T10	6		T11	1		T5	478
valid_sources[0x38]	10965	1			T2	1		T10	15		T11	3
valid_sources[0x39]	11451	1			T2	2		T11	1		T5	478
valid_sources[0x3a]	11610	1			T2	3		T10	8		T5	472
valid_sources[0x3b]	11300	1			T2	1		T10	5		T11	1
valid_sources[0x3c]	11240	1			T2	1		T10	10		T11	7
valid_sources[0x3d]	18896	1			T2	3		T10	3		T11	3
valid_sources[0x3e]	12367	1			T2	6		T10	4		T5	496
valid_sources[0x3f]	13190	1			T2	1		T5	454		T13	4
valid_sources[0x40]	13503	1			T2	3		T10	6		T11	2
valid_sources[0x41]	12155	1			T2	1		T10	14		T11	6
valid_sources[0x42]	11575	1			T2	3		T10	1		T11	2
valid_sources[0x43]	13933	1			T2	5		T10	4		T11	2
valid_sources[0x44]	11138	1			T2	8		T10	3		T11	4
valid_sources[0x45]	11369	1			T10	2		T11	6		T5	507
valid_sources[0x46]	11452	1			T2	3		T10	7		T5	519
valid_sources[0x47]	11716	1			T2	1		T10	9		T11	7
valid_sources[0x48]	12129	1			T2	3		T10	4		T11	4
valid_sources[0x49]	15017	1			T2	1		T10	2		T11	4
valid_sources[0x4a]	15489	1			T2	1		T10	7		T5	559
valid_sources[0x4b]	11460	1			T10	1		T11	6		T5	505
valid_sources[0x4c]	11570	1			T2	3		T10	7		T11	7
valid_sources[0x4d]	11640	1			T2	1		T10	2		T11	5
valid_sources[0x4e]	10882	1			T2	1		T5	459		T13	4
valid_sources[0x4f]	11813	1			T2	2		T10	3		T11	2
valid_sources[0x50]	11446	1			T10	8		T11	1		T5	483
valid_sources[0x51]	10775	1			T2	6		T10	3		T11	4
valid_sources[0x52]	11362	1			T2	4		T10	1		T11	6
valid_sources[0x53]	12580	1			T2	4		T11	2		T5	494
valid_sources[0x54]	11498	1			T2	3		T10	6		T5	493
valid_sources[0x55]	11473	1			T2	5		T10	2		T11	2
valid_sources[0x56]	11203	1			T2	2		T10	4		T11	4
valid_sources[0x57]	11140	1			T2	3		T10	5		T11	1
valid_sources[0x58]	12194	1			T2	2		T10	6		T11	2
valid_sources[0x59]	16680	1			T2	5		T10	5		T5	472
valid_sources[0x5a]	13809	1			T2	7		T10	4		T11	6
valid_sources[0x5b]	11595	1			T2	5		T10	3		T5	481
valid_sources[0x5c]	11251	1			T2	1		T11	27		T5	498
valid_sources[0x5d]	11405	1			T10	4		T11	1		T5	464
valid_sources[0x5e]	11405	1			T10	3		T11	1		T5	480
valid_sources[0x5f]	11174	1			T2	8		T10	3		T11	4
valid_sources[0x60]	12823	1			T5	473		T13	5		T17	3
valid_sources[0x61]	11383	1			T2	4		T11	5		T5	509
valid_sources[0x62]	11105	1			T10	2		T11	1		T5	530
valid_sources[0x63]	12977	1			T2	2		T11	1		T5	464
valid_sources[0x64]	11195	1			T2	4		T10	5		T11	5
valid_sources[0x65]	21849	1			T11	3		T5	495		T13	3
valid_sources[0x66]	12101	1			T2	4		T10	15		T5	503
valid_sources[0x67]	12445	1			T2	4		T10	5		T11	4
valid_sources[0x68]	11123	1			T2	3		T10	12		T11	8
valid_sources[0x69]	11363	1			T2	5		T11	3		T5	516
valid_sources[0x6a]	11242	1			T2	5		T10	2		T11	1
valid_sources[0x6b]	15021	1			T2	3		T10	3		T11	1
valid_sources[0x6c]	12989	1			T2	2		T10	4		T11	10
valid_sources[0x6d]	11862	1			T2	2		T10	2		T11	2
valid_sources[0x6e]	12191	1			T2	1		T10	3		T11	6
valid_sources[0x6f]	11285	1			T2	1		T10	3		T11	3
valid_sources[0x70]	12646	1			T2	3		T10	15		T11	1
valid_sources[0x71]	10685	1			T2	3		T10	14		T11	7
valid_sources[0x72]	13833	1			T2	4		T11	6		T5	510
valid_sources[0x73]	11696	1			T10	10		T11	2		T5	483
valid_sources[0x74]	11751	1			T2	8		T10	7		T5	457
valid_sources[0x75]	11093	1			T11	7		T5	474		T13	6
valid_sources[0x76]	11762	1			T10	4		T5	442		T13	1
valid_sources[0x77]	11382	1			T2	2		T10	6		T11	10
valid_sources[0x78]	12532	1			T10	12		T11	1		T5	490
valid_sources[0x79]	12504	1			T10	13		T11	1		T5	471
valid_sources[0x7a]	12323	1			T2	4		T10	10		T11	6
valid_sources[0x7b]	10929	1			T2	3		T11	6		T5	536
valid_sources[0x7c]	11356	1			T10	6		T11	4		T5	496
valid_sources[0x7d]	11294	1			T2	2		T10	1		T11	8
valid_sources[0x7e]	11511	1			T2	1		T10	2		T11	7
valid_sources[0x7f]	11481	1			T2	2		T10	4		T11	12
valid_sources[0x80]	11521	1			T2	6		T11	2		T5	533

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1631894

1

T1

51

T2

245

T10

287

values[0x0]

all_enables

biggest_size

148165

1

T1

55

T2

86

T3

5

values[0x1]

all_enables

biggest_size

147899

1

T1

55

T2

75

T3

4