Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	106027286	15048	0	0
claim_transition_if_regwen_rd_A	106027286	1208	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106027286	15048	0	0
T5	865287	8	0	0
T13	20393	0	0	0
T14	26556	0	0	0
T15	5606	0	0	0
T17	23824	0	0	0
T18	164942	0	0	0
T19	34499	0	0	0
T20	25165	0	0	0
T21	164022	0	0	0
T39	0	4	0	0
T40	0	12	0	0
T41	0	5	0	0
T49	0	6	0	0
T51	1614	0	0	0
T78	0	2	0	0
T93	0	3	0	0
T130	0	9	0	0
T131	0	6	0	0
T132	0	1	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106027286	1208	0	0
T39	248912	10	0	0
T58	191167	0	0	0
T69	3413	0	0	0
T94	0	17	0	0
T95	0	15	0	0
T105	0	118	0	0
T114	0	8	0	0
T133	0	8	0	0
T134	0	6	0	0
T135	0	4	0	0
T136	0	2	0	0
T137	0	9	0	0
T138	1680	0	0	0
T139	38025	0	0	0
T140	8373	0	0	0
T141	252638	0	0	0
T142	1417	0	0	0
T143	100274	0	0	0
T144	1186	0	0	0