Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1982838	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2197904

1

T1

755

T2

553

T3

1623

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3846193	1			T1	636		T2	458		T3	1909
values[0x0]	166950	1			T1	318		T2	215		T3	366
values[0x1]	167599	1			T1	266		T2	217		T3	402

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1576814	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2603928

1

T1

882

T2

642

T3

1849

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14297	1			T1	8		T12	12		T14	22
valid_sources[0x01]	15072	1			T1	5		T2	2		T12	3
valid_sources[0x02]	14367	1			T1	3		T2	4		T12	6
valid_sources[0x03]	15769	1			T1	4		T2	8		T12	3
valid_sources[0x04]	13476	1			T1	6		T12	3		T14	16
valid_sources[0x05]	14717	1			T1	8		T2	10		T12	4
valid_sources[0x06]	13848	1			T1	4		T2	4		T12	3
valid_sources[0x07]	13974	1			T1	12		T12	5		T14	9
valid_sources[0x08]	13869	1			T1	5		T2	9		T12	7
valid_sources[0x09]	14236	1			T1	8		T2	6		T12	11
valid_sources[0x0a]	13884	1			T1	2		T2	2		T12	6
valid_sources[0x0b]	14242	1			T1	5		T2	7		T12	4
valid_sources[0x0c]	13921	1			T1	3		T12	7		T14	22
valid_sources[0x0d]	13831	1			T1	3		T2	3		T12	8
valid_sources[0x0e]	14549	1			T1	3		T12	3		T14	6
valid_sources[0x0f]	13804	1			T2	20		T12	3		T14	4
valid_sources[0x10]	13873	1			T1	4		T2	14		T12	6
valid_sources[0x11]	13801	1			T1	7		T2	1		T12	3
valid_sources[0x12]	17995	1			T1	4		T2	1		T12	5
valid_sources[0x13]	13692	1			T2	9		T12	5		T14	11
valid_sources[0x14]	14966	1			T1	6		T12	5		T14	14
valid_sources[0x15]	13592	1			T1	2		T2	1		T12	6
valid_sources[0x16]	13697	1			T1	7		T2	1		T11	2
valid_sources[0x17]	13880	1			T1	5		T2	6		T12	3
valid_sources[0x18]	14628	1			T1	6		T12	3		T14	15
valid_sources[0x19]	13369	1			T1	6		T12	8		T14	10
valid_sources[0x1a]	13512	1			T1	4		T2	1		T12	3
valid_sources[0x1b]	13860	1			T1	2		T2	8		T12	1
valid_sources[0x1c]	14176	1			T1	8		T2	5		T12	11
valid_sources[0x1d]	14528	1			T1	2		T2	4		T12	6
valid_sources[0x1e]	15273	1			T1	6		T2	10		T11	1
valid_sources[0x1f]	15364	1			T1	8		T2	1		T12	6
valid_sources[0x20]	13560	1			T1	4		T12	9		T14	10
valid_sources[0x21]	13905	1			T1	5		T12	4		T14	9
valid_sources[0x22]	14020	1			T1	7		T2	7		T12	4
valid_sources[0x23]	14893	1			T1	4		T2	4		T12	3
valid_sources[0x24]	16463	1			T1	8		T12	10		T14	15
valid_sources[0x25]	13898	1			T1	2		T2	3		T12	1
valid_sources[0x26]	17476	1			T1	6		T2	1		T12	2
valid_sources[0x27]	14155	1			T1	3		T2	5		T12	5
valid_sources[0x28]	13784	1			T1	3		T2	4		T12	8
valid_sources[0x29]	13415	1			T1	9		T2	2		T12	9
valid_sources[0x2a]	13591	1			T1	10		T2	9		T12	3
valid_sources[0x2b]	15733	1			T1	6		T2	12		T12	5
valid_sources[0x2c]	14063	1			T1	5		T2	8		T12	8
valid_sources[0x2d]	51899	1			T1	4		T2	7		T12	14
valid_sources[0x2e]	13496	1			T1	5		T2	1		T12	1
valid_sources[0x2f]	13547	1			T1	2		T2	7		T12	3
valid_sources[0x30]	13503	1			T1	1		T2	12		T12	2
valid_sources[0x31]	13947	1			T1	2		T2	4		T11	1
valid_sources[0x32]	15670	1			T1	7		T2	9		T12	3
valid_sources[0x33]	21913	1			T1	2		T2	3		T12	6
valid_sources[0x34]	19052	1			T1	6		T2	1		T12	6
valid_sources[0x35]	13977	1			T1	6		T11	1		T12	5
valid_sources[0x36]	13584	1			T1	7		T2	6		T12	5
valid_sources[0x37]	13787	1			T1	3		T2	3		T12	5
valid_sources[0x38]	14872	1			T1	8		T2	5		T12	4
valid_sources[0x39]	15686	1			T1	6		T2	4		T12	7
valid_sources[0x3a]	33760	1			T1	8		T12	5		T14	12
valid_sources[0x3b]	14380	1			T1	3		T12	10		T14	17
valid_sources[0x3c]	42407	1			T1	3		T2	13		T12	5
valid_sources[0x3d]	13967	1			T1	5		T2	4		T12	2
valid_sources[0x3e]	13765	1			T1	1		T2	7		T12	7
valid_sources[0x3f]	14225	1			T1	4		T11	3		T12	8
valid_sources[0x40]	14251	1			T1	4		T12	9		T14	15
valid_sources[0x41]	13789	1			T1	7		T2	1		T12	9
valid_sources[0x42]	14351	1			T1	7		T2	3		T12	9
valid_sources[0x43]	13904	1			T1	6		T12	2		T14	15
valid_sources[0x44]	15378	1			T2	3		T12	6		T14	6
valid_sources[0x45]	20559	1			T1	5		T2	2		T12	2
valid_sources[0x46]	13739	1			T1	3		T2	3		T12	11
valid_sources[0x47]	15799	1			T1	5		T12	10		T14	10
valid_sources[0x48]	13998	1			T2	7		T12	1		T14	9
valid_sources[0x49]	14169	1			T1	7		T2	1		T12	6
valid_sources[0x4a]	13944	1			T1	2		T12	8		T14	14
valid_sources[0x4b]	14301	1			T1	6		T12	5		T14	14
valid_sources[0x4c]	23379	1			T1	2		T2	1		T14	18
valid_sources[0x4d]	13719	1			T1	6		T12	6		T14	18
valid_sources[0x4e]	14468	1			T1	7		T2	3		T12	11
valid_sources[0x4f]	15750	1			T1	4		T12	10		T14	16
valid_sources[0x50]	13701	1			T1	11		T12	6		T14	10
valid_sources[0x51]	14123	1			T1	5		T2	4		T12	3
valid_sources[0x52]	13691	1			T1	3		T2	15		T12	4
valid_sources[0x53]	16555	1			T1	5		T2	9		T12	11
valid_sources[0x54]	13405	1			T1	4		T2	10		T12	2
valid_sources[0x55]	13969	1			T1	5		T2	1		T12	8
valid_sources[0x56]	13646	1			T1	3		T2	4		T12	8
valid_sources[0x57]	13922	1			T1	2		T12	7		T14	18
valid_sources[0x58]	13444	1			T1	5		T2	1		T12	7
valid_sources[0x59]	13394	1			T1	7		T2	4		T12	6
valid_sources[0x5a]	16988	1			T1	7		T12	7		T14	14
valid_sources[0x5b]	13340	1			T1	5		T2	5		T12	4
valid_sources[0x5c]	14283	1			T1	5		T2	3		T12	12
valid_sources[0x5d]	15239	1			T1	4		T2	3		T12	14
valid_sources[0x5e]	13817	1			T1	6		T12	1		T14	14
valid_sources[0x5f]	14711	1			T1	5		T12	3		T14	9
valid_sources[0x60]	14516	1			T1	2		T2	5		T12	2
valid_sources[0x61]	13787	1			T1	4		T2	1		T11	1
valid_sources[0x62]	15282	1			T1	2		T12	9		T14	11
valid_sources[0x63]	14119	1			T1	6		T2	2		T11	2
valid_sources[0x64]	13682	1			T1	8		T12	8		T14	10
valid_sources[0x65]	13776	1			T1	12		T12	4		T14	12
valid_sources[0x66]	14622	1			T1	4		T2	6		T12	7
valid_sources[0x67]	125620	1			T1	4		T2	12		T12	7
valid_sources[0x68]	16853	1			T1	5		T2	2		T12	6
valid_sources[0x69]	23564	1			T1	6		T12	7		T14	13
valid_sources[0x6a]	13547	1			T1	8		T2	2		T12	6
valid_sources[0x6b]	14900	1			T1	6		T2	1		T12	5
valid_sources[0x6c]	14092	1			T1	4		T2	1		T12	6
valid_sources[0x6d]	13716	1			T1	6		T2	1		T12	1
valid_sources[0x6e]	13992	1			T1	2		T2	17		T12	10
valid_sources[0x6f]	13360	1			T1	1		T2	1		T12	6
valid_sources[0x70]	14208	1			T1	9		T12	5		T14	17
valid_sources[0x71]	13643	1			T1	5		T2	4		T12	7
valid_sources[0x72]	14268	1			T1	14		T2	15		T12	6
valid_sources[0x73]	13599	1			T1	5		T2	5		T12	2
valid_sources[0x74]	14221	1			T1	6		T12	7		T14	15
valid_sources[0x75]	14152	1			T1	9		T2	9		T11	2
valid_sources[0x76]	14125	1			T1	7		T2	4		T12	5
valid_sources[0x77]	14346	1			T1	4		T11	3		T12	10
valid_sources[0x78]	14570	1			T1	1		T2	5		T12	9
valid_sources[0x79]	19415	1			T1	5		T2	6		T12	5
valid_sources[0x7a]	26737	1			T1	6		T2	4		T12	4
valid_sources[0x7b]	76678	1			T1	7		T2	6		T12	5
valid_sources[0x7c]	13996	1			T1	6		T12	12		T14	23
valid_sources[0x7d]	13487	1			T1	2		T2	1		T12	8
valid_sources[0x7e]	13139	1			T1	5		T12	5		T14	15
valid_sources[0x7f]	16587	1			T1	2		T12	5		T14	16
valid_sources[0x80]	13479	1			T1	7		T12	8		T14	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1909728

1

T1

248

T2

180

T3

941

values[0x0]

all_enables

biggest_size

144595

1

T1

281

T2

188

T3

321

values[0x1]

all_enables

biggest_size

143581

1

T1

226

T2

185

T3

361