Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	106529039	14125	0	0
claim_transition_if_regwen_rd_A	106529039	1496	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106529039	14125	0	0
T21	213555	4	0	0
T25	111464	0	0	0
T36	0	14	0	0
T55	11816	0	0	0
T57	0	1	0	0
T73	0	4	0	0
T96	0	1	0	0
T100	0	9	0	0
T134	0	2	0	0
T135	0	5	0	0
T136	0	8	0	0
T137	0	8	0	0
T138	6857	0	0	0
T139	29947	0	0	0
T140	4904	0	0	0
T141	6190	0	0	0
T142	8487	0	0	0
T143	23166	0	0	0
T144	31798	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106529039	1496	0	0
T97	0	17	0	0
T103	0	16	0	0
T108	0	43	0	0
T110	0	10	0	0
T133	0	4	0	0
T134	365711	11	0	0
T145	0	2	0	0
T146	0	13	0	0
T147	0	17	0	0
T148	0	33	0	0
T149	12609	0	0	0
T150	1948	0	0	0
T151	11112	0	0	0
T152	321070	0	0	0
T153	44960	0	0	0
T154	2306	0	0	0
T155	1293	0	0	0
T156	30361	0	0	0
T157	1341	0	0	0