Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2048940	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2270852

1

T2

5

T3

659

T4

719

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3969299	1			T2	10		T3	570		T4	431
values[0x0]	174782	1			T2	4		T3	271		T4	285
values[0x1]	175711	1			T2	4		T3	241		T4	323

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1629125	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2690667

1

T2

8

T3

750

T4

798

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12542	1			T3	3		T11	5		T12	1
valid_sources[0x01]	14428	1			T3	4		T4	1		T11	7
valid_sources[0x02]	14642	1			T3	4		T4	3		T11	13
valid_sources[0x03]	13683	1			T3	4		T4	1		T11	5
valid_sources[0x04]	153337	1			T3	3		T11	16		T14	8
valid_sources[0x05]	12635	1			T3	3		T4	2		T11	3
valid_sources[0x06]	14731	1			T2	1		T3	7		T4	1
valid_sources[0x07]	12788	1			T3	2		T4	3		T11	17
valid_sources[0x08]	12648	1			T3	5		T4	1		T11	5
valid_sources[0x09]	14305	1			T3	2		T11	8		T14	1
valid_sources[0x0a]	13202	1			T3	10		T4	1		T11	7
valid_sources[0x0b]	12308	1			T3	3		T11	11		T14	6
valid_sources[0x0c]	14439	1			T3	2		T11	7		T14	5
valid_sources[0x0d]	12725	1			T3	7		T4	5		T11	8
valid_sources[0x0e]	12648	1			T3	3		T4	4		T11	5
valid_sources[0x0f]	13106	1			T3	6		T4	1		T11	11
valid_sources[0x10]	13003	1			T3	1		T11	7		T14	4
valid_sources[0x11]	12332	1			T3	4		T4	11		T11	13
valid_sources[0x12]	12887	1			T3	3		T11	10		T12	1
valid_sources[0x13]	12464	1			T3	5		T4	21		T11	9
valid_sources[0x14]	12304	1			T3	6		T4	7		T11	11
valid_sources[0x15]	13032	1			T3	4		T4	4		T11	11
valid_sources[0x16]	14200	1			T3	1		T11	5		T12	5
valid_sources[0x17]	12408	1			T3	5		T11	7		T12	2
valid_sources[0x18]	12965	1			T3	2		T4	6		T11	12
valid_sources[0x19]	13103	1			T3	3		T4	6		T11	10
valid_sources[0x1a]	12524	1			T3	6		T4	17		T11	17
valid_sources[0x1b]	30959	1			T3	6		T4	4		T11	11
valid_sources[0x1c]	12463	1			T2	1		T3	6		T4	7
valid_sources[0x1d]	13457	1			T3	5		T4	8		T11	8
valid_sources[0x1e]	11807	1			T3	3		T4	5		T11	5
valid_sources[0x1f]	12639	1			T3	3		T4	5		T11	7
valid_sources[0x20]	12617	1			T3	5		T4	1		T11	6
valid_sources[0x21]	12511	1			T3	8		T11	8		T12	1
valid_sources[0x22]	12924	1			T3	5		T4	9		T11	13
valid_sources[0x23]	15509	1			T3	2		T11	4		T20	15
valid_sources[0x24]	12775	1			T3	3		T4	6		T11	6
valid_sources[0x25]	13132	1			T3	3		T4	7		T11	9
valid_sources[0x26]	12456	1			T3	6		T4	11		T11	5
valid_sources[0x27]	12763	1			T2	1		T3	6		T11	2
valid_sources[0x28]	12565	1			T3	5		T4	9		T11	6
valid_sources[0x29]	12389	1			T3	6		T4	4		T11	5
valid_sources[0x2a]	12712	1			T3	4		T11	6		T12	1
valid_sources[0x2b]	12774	1			T3	1		T11	7		T12	3
valid_sources[0x2c]	12460	1			T3	3		T11	13		T14	13
valid_sources[0x2d]	13193	1			T3	6		T4	2		T11	10
valid_sources[0x2e]	13781	1			T4	1		T11	6		T12	1
valid_sources[0x2f]	12466	1			T3	6		T4	6		T11	13
valid_sources[0x30]	12919	1			T3	3		T4	1		T11	5
valid_sources[0x31]	12249	1			T3	7		T4	7		T11	14
valid_sources[0x32]	12450	1			T3	6		T4	19		T11	9
valid_sources[0x33]	171651	1			T3	5		T4	1		T11	6
valid_sources[0x34]	12762	1			T3	3		T4	8		T11	3
valid_sources[0x35]	13798	1			T3	7		T4	11		T11	8
valid_sources[0x36]	12600	1			T3	4		T4	7		T11	6
valid_sources[0x37]	12352	1			T3	2		T11	7		T12	1
valid_sources[0x38]	12060	1			T3	6		T4	2		T11	5
valid_sources[0x39]	18487	1			T3	5		T4	5		T11	9
valid_sources[0x3a]	13257	1			T3	5		T4	6		T11	9
valid_sources[0x3b]	12674	1			T3	4		T4	2		T11	4
valid_sources[0x3c]	13979	1			T3	7		T11	4		T12	3
valid_sources[0x3d]	26829	1			T3	2		T11	15		T12	2
valid_sources[0x3e]	20787	1			T3	6		T4	5		T11	6
valid_sources[0x3f]	12769	1			T3	3		T4	4		T11	8
valid_sources[0x40]	13153	1			T3	3		T4	3		T11	7
valid_sources[0x41]	12225	1			T3	4		T4	3		T11	8
valid_sources[0x42]	13615	1			T3	2		T4	2		T11	7
valid_sources[0x43]	12443	1			T3	2		T4	6		T11	8
valid_sources[0x44]	13046	1			T3	12		T11	8		T12	1
valid_sources[0x45]	12777	1			T3	1		T4	1		T11	8
valid_sources[0x46]	13562	1			T3	3		T4	7		T11	5
valid_sources[0x47]	12690	1			T2	1		T3	2		T11	8
valid_sources[0x48]	21412	1			T3	6		T11	13		T12	2
valid_sources[0x49]	62218	1			T2	1		T3	2		T11	11
valid_sources[0x4a]	12510	1			T3	4		T11	7		T12	1
valid_sources[0x4b]	15223	1			T3	1		T4	7		T11	11
valid_sources[0x4c]	12316	1			T3	4		T4	5		T11	10
valid_sources[0x4d]	12649	1			T3	1		T11	9		T14	7
valid_sources[0x4e]	13145	1			T3	10		T4	14		T11	10
valid_sources[0x4f]	12642	1			T3	3		T4	2		T11	8
valid_sources[0x50]	12417	1			T3	9		T11	9		T12	1
valid_sources[0x51]	15322	1			T2	1		T3	4		T4	3
valid_sources[0x52]	12752	1			T2	1		T3	3		T4	8
valid_sources[0x53]	12459	1			T3	3		T4	2		T11	2
valid_sources[0x54]	12466	1			T3	5		T4	2		T11	9
valid_sources[0x55]	13269	1			T3	3		T4	8		T11	13
valid_sources[0x56]	12517	1			T2	1		T3	1		T4	7
valid_sources[0x57]	14032	1			T3	9		T4	7		T11	10
valid_sources[0x58]	12939	1			T3	5		T11	6		T12	2
valid_sources[0x59]	12987	1			T3	3		T4	2		T11	8
valid_sources[0x5a]	12038	1			T3	4		T4	4		T11	11
valid_sources[0x5b]	12590	1			T3	2		T4	7		T11	8
valid_sources[0x5c]	12888	1			T2	1		T3	9		T4	4
valid_sources[0x5d]	12636	1			T3	3		T4	1		T11	6
valid_sources[0x5e]	14070	1			T3	1		T4	2		T11	6
valid_sources[0x5f]	13926	1			T3	5		T4	1		T11	5
valid_sources[0x60]	18265	1			T3	10		T11	10		T12	2
valid_sources[0x61]	12584	1			T3	15		T4	9		T11	6
valid_sources[0x62]	15029	1			T3	2		T11	9		T14	5
valid_sources[0x63]	12182	1			T3	3		T4	4		T11	6
valid_sources[0x64]	12747	1			T3	1		T4	5		T11	15
valid_sources[0x65]	13113	1			T3	4		T11	10		T12	2
valid_sources[0x66]	13109	1			T3	9		T4	9		T11	9
valid_sources[0x67]	14137	1			T3	5		T4	11		T11	5
valid_sources[0x68]	14370	1			T3	4		T4	4		T11	6
valid_sources[0x69]	14909	1			T3	6		T4	5		T11	9
valid_sources[0x6a]	13601	1			T3	4		T4	5		T11	6
valid_sources[0x6b]	18907	1			T3	2		T4	9		T11	15
valid_sources[0x6c]	12617	1			T3	5		T4	3		T11	8
valid_sources[0x6d]	12026	1			T3	3		T11	13		T14	7
valid_sources[0x6e]	14626	1			T3	6		T4	2		T11	7
valid_sources[0x6f]	12828	1			T3	3		T4	4		T11	3
valid_sources[0x70]	75689	1			T3	1		T11	12		T14	6
valid_sources[0x71]	13166	1			T3	4		T4	3		T11	7
valid_sources[0x72]	12406	1			T3	3		T4	10		T11	5
valid_sources[0x73]	12719	1			T3	8		T4	4		T11	10
valid_sources[0x74]	12150	1			T3	8		T4	9		T11	11
valid_sources[0x75]	12552	1			T3	3		T4	1		T11	12
valid_sources[0x76]	12526	1			T3	7		T4	1		T11	7
valid_sources[0x77]	14210	1			T4	5		T11	9		T12	2
valid_sources[0x78]	12406	1			T2	1		T3	3		T11	3
valid_sources[0x79]	13235	1			T3	2		T11	7		T12	1
valid_sources[0x7a]	12732	1			T3	3		T4	1		T11	13
valid_sources[0x7b]	12283	1			T3	3		T4	7		T11	8
valid_sources[0x7c]	12061	1			T3	9		T4	2		T11	9
valid_sources[0x7d]	15396	1			T3	8		T11	9		T12	1
valid_sources[0x7e]	12801	1			T3	3		T4	2		T11	11
valid_sources[0x7f]	15710	1			T3	7		T4	5		T11	7
valid_sources[0x80]	12335	1			T3	2		T4	19		T11	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1969042

1

T3

218

T4

192

T11

633

values[0x0]

all_enables

biggest_size

151534

1

T2

3

T3

235

T4

248

values[0x1]

all_enables

biggest_size

150276

1

T2

2

T3

206

T4

279