Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	117862572	14885	0	0
claim_transition_if_regwen_rd_A	117862572	1459	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117862572	14885	0	0
T18	88326	0	0	0
T19	681495	0	0	0
T54	23005	0	0	0
T57	44325	0	0	0
T63	116113	4	0	0
T91	0	1	0	0
T92	0	2	0	0
T105	0	2	0	0
T150	0	8	0	0
T151	0	5	0	0
T152	0	3	0	0
T153	0	11	0	0
T154	0	16	0	0
T155	0	6	0	0
T156	1173	0	0	0
T157	1026	0	0	0
T158	680	0	0	0
T159	3208	0	0	0
T160	43279	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117862572	1459	0	0
T92	178581	1	0	0
T161	0	8	0	0
T162	0	12	0	0
T163	0	2	0	0
T164	0	18	0	0
T165	0	5	0	0
T166	0	25	0	0
T167	0	58	0	0
T168	0	143	0	0
T169	0	18	0	0
T170	28761	0	0	0
T171	723	0	0	0
T172	4665	0	0	0
T173	128286	0	0	0
T174	28348	0	0	0
T175	1118	0	0	0
T176	81735	0	0	0
T177	7529	0	0	0
T178	1663	0	0	0