Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1977959	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2196287

1

T1

194

T3

245

T10

277

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3839877	1			T1	195		T3	192		T10	227
values[0x0]	166543	1			T1	57		T3	89		T10	114
values[0x1]	167826	1			T1	63		T3	95		T10	94

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1573192	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2601054

1

T1

218

T3

274

T10

315

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13071	1			T1	4		T10	5		T5	1224
valid_sources[0x01]	13336	1			T1	3		T3	2		T10	6
valid_sources[0x02]	13315	1			T1	2		T5	1214		T11	425
valid_sources[0x03]	13303	1			T1	1		T10	3		T5	1221
valid_sources[0x04]	13324	1			T1	15		T5	1175		T11	464
valid_sources[0x05]	15656	1			T1	2		T3	5		T10	3
valid_sources[0x06]	14567	1			T5	1261		T11	434		T12	6
valid_sources[0x07]	13497	1			T1	1		T5	1205		T11	435
valid_sources[0x08]	55188	1			T1	1		T10	3		T5	1149
valid_sources[0x09]	13417	1			T10	1		T5	1174		T11	458
valid_sources[0x0a]	19296	1			T3	1		T10	2		T5	1170
valid_sources[0x0b]	13985	1			T3	7		T5	1181		T11	461
valid_sources[0x0c]	19535	1			T5	1169		T11	490		T12	12
valid_sources[0x0d]	13184	1			T5	1214		T11	452		T12	2
valid_sources[0x0e]	14023	1			T5	1257		T11	421		T12	4
valid_sources[0x0f]	13127	1			T1	1		T10	8		T5	1220
valid_sources[0x10]	15376	1			T10	3		T5	1196		T11	454
valid_sources[0x11]	13815	1			T3	5		T10	4		T5	1201
valid_sources[0x12]	15281	1			T10	4		T5	1167		T11	481
valid_sources[0x13]	13468	1			T1	1		T3	3		T5	1167
valid_sources[0x14]	13291	1			T1	3		T5	1195		T11	455
valid_sources[0x15]	13407	1			T10	3		T5	1232		T11	432
valid_sources[0x16]	13681	1			T3	3		T5	1142		T11	481
valid_sources[0x17]	18194	1			T1	1		T10	2		T5	1269
valid_sources[0x18]	13543	1			T5	1232		T11	464		T12	5
valid_sources[0x19]	13201	1			T3	6		T5	1121		T11	472
valid_sources[0x1a]	14232	1			T1	1		T3	2		T5	1176
valid_sources[0x1b]	16100	1			T10	1		T5	1168		T11	480
valid_sources[0x1c]	14931	1			T1	3		T5	1214		T11	486
valid_sources[0x1d]	29115	1			T1	1		T10	5		T5	1130
valid_sources[0x1e]	13333	1			T10	3		T5	1176		T11	505
valid_sources[0x1f]	13998	1			T1	1		T3	2		T10	2
valid_sources[0x20]	14012	1			T3	2		T10	5		T5	1157
valid_sources[0x21]	13310	1			T1	1		T3	1		T10	1
valid_sources[0x22]	13611	1			T5	1219		T11	455		T12	3
valid_sources[0x23]	12910	1			T3	6		T10	1		T5	1191
valid_sources[0x24]	13426	1			T1	2		T10	3		T5	1189
valid_sources[0x25]	13065	1			T5	1195		T11	461		T12	7
valid_sources[0x26]	13480	1			T3	9		T10	2		T5	1195
valid_sources[0x27]	13257	1			T10	5		T5	1215		T11	471
valid_sources[0x28]	13360	1			T3	1		T5	1136		T11	500
valid_sources[0x29]	13498	1			T10	2		T5	1197		T11	473
valid_sources[0x2a]	13062	1			T1	2		T5	1237		T11	451
valid_sources[0x2b]	13347	1			T10	1		T5	1172		T11	441
valid_sources[0x2c]	13434	1			T1	4		T3	3		T10	1
valid_sources[0x2d]	13414	1			T1	4		T3	14		T5	1218
valid_sources[0x2e]	13379	1			T1	7		T5	1119		T11	469
valid_sources[0x2f]	24638	1			T1	1		T10	3		T5	1143
valid_sources[0x30]	13294	1			T10	1		T5	1273		T11	472
valid_sources[0x31]	14011	1			T10	1		T5	1190		T11	467
valid_sources[0x32]	13171	1			T1	2		T5	1181		T11	478
valid_sources[0x33]	13743	1			T1	3		T10	2		T5	1178
valid_sources[0x34]	15637	1			T10	2		T5	1188		T11	468
valid_sources[0x35]	12998	1			T5	1283		T11	422		T12	6
valid_sources[0x36]	13652	1			T10	2		T5	1189		T11	459
valid_sources[0x37]	74984	1			T5	1193		T11	439		T12	14
valid_sources[0x38]	13264	1			T10	4		T5	1201		T11	452
valid_sources[0x39]	15187	1			T10	1		T5	1133		T11	440
valid_sources[0x3a]	13506	1			T10	3		T5	1182		T11	440
valid_sources[0x3b]	13668	1			T1	4		T3	1		T5	1208
valid_sources[0x3c]	14351	1			T1	1		T3	2		T5	1152
valid_sources[0x3d]	15254	1			T1	2		T10	2		T5	1121
valid_sources[0x3e]	15171	1			T1	5		T3	5		T5	1198
valid_sources[0x3f]	33282	1			T1	1		T5	1184		T11	443
valid_sources[0x40]	13505	1			T1	2		T3	7		T10	4
valid_sources[0x41]	58516	1			T5	1203		T11	451		T12	6
valid_sources[0x42]	15232	1			T5	1186		T11	440		T12	1
valid_sources[0x43]	13356	1			T3	3		T5	1202		T11	453
valid_sources[0x44]	13073	1			T1	1		T3	4		T5	1143
valid_sources[0x45]	20762	1			T5	1134		T11	445		T12	5
valid_sources[0x46]	13868	1			T1	2		T10	6		T5	1212
valid_sources[0x47]	13413	1			T10	2		T5	1209		T11	437
valid_sources[0x48]	13986	1			T5	1164		T11	469		T12	1
valid_sources[0x49]	13759	1			T5	1193		T11	429		T12	4
valid_sources[0x4a]	13197	1			T1	5		T5	1239		T11	411
valid_sources[0x4b]	14427	1			T5	1184		T11	443		T12	7
valid_sources[0x4c]	13104	1			T10	1		T5	1178		T11	429
valid_sources[0x4d]	19013	1			T1	6		T10	3		T5	1194
valid_sources[0x4e]	15981	1			T1	6		T3	7		T10	2
valid_sources[0x4f]	13142	1			T10	2		T5	1187		T11	437
valid_sources[0x50]	13372	1			T3	7		T5	1157		T11	486
valid_sources[0x51]	13535	1			T1	6		T10	2		T5	1158
valid_sources[0x52]	13528	1			T5	1261		T11	447		T12	3
valid_sources[0x53]	12903	1			T10	1		T5	1171		T11	455
valid_sources[0x54]	13565	1			T10	1		T5	1138		T11	454
valid_sources[0x55]	13425	1			T10	1		T5	1167		T11	497
valid_sources[0x56]	17418	1			T5	1151		T11	493		T12	6
valid_sources[0x57]	13007	1			T5	1160		T11	472		T12	2
valid_sources[0x58]	14896	1			T5	1168		T11	472		T12	4
valid_sources[0x59]	15105	1			T1	5		T10	8		T5	1194
valid_sources[0x5a]	14961	1			T1	2		T3	5		T10	1
valid_sources[0x5b]	13191	1			T3	14		T10	9		T5	1162
valid_sources[0x5c]	23026	1			T1	1		T3	12		T5	1207
valid_sources[0x5d]	13448	1			T3	2		T10	2		T5	1173
valid_sources[0x5e]	13489	1			T1	4		T3	2		T5	1194
valid_sources[0x5f]	112135	1			T1	1		T5	1118		T11	490
valid_sources[0x60]	13471	1			T5	1111		T11	465		T12	14
valid_sources[0x61]	13409	1			T1	2		T10	2		T5	1166
valid_sources[0x62]	13257	1			T3	4		T5	1190		T11	422
valid_sources[0x63]	14113	1			T1	2		T5	1174		T11	485
valid_sources[0x64]	14458	1			T10	2		T5	1148		T11	521
valid_sources[0x65]	13853	1			T1	2		T10	3		T5	1193
valid_sources[0x66]	14461	1			T1	1		T10	1		T5	1202
valid_sources[0x67]	14145	1			T1	4		T3	5		T5	1165
valid_sources[0x68]	13410	1			T1	4		T3	2		T10	4
valid_sources[0x69]	13137	1			T3	10		T10	2		T5	1250
valid_sources[0x6a]	13831	1			T3	2		T5	1230		T11	465
valid_sources[0x6b]	13785	1			T5	1188		T11	468		T12	7
valid_sources[0x6c]	13425	1			T3	7		T10	4		T5	1187
valid_sources[0x6d]	14801	1			T5	1154		T11	441		T12	5
valid_sources[0x6e]	13583	1			T1	1		T5	1172		T11	418
valid_sources[0x6f]	13185	1			T1	1		T3	1		T5	1182
valid_sources[0x70]	13517	1			T10	5		T5	1217		T11	451
valid_sources[0x71]	13205	1			T10	5		T5	1246		T11	449
valid_sources[0x72]	13340	1			T10	3		T5	1197		T11	497
valid_sources[0x73]	56605	1			T10	1		T5	1130		T11	463
valid_sources[0x74]	16076	1			T1	7		T3	9		T5	1226
valid_sources[0x75]	13775	1			T1	7		T3	2		T10	1
valid_sources[0x76]	16341	1			T5	1149		T11	499		T12	5
valid_sources[0x77]	16455	1			T1	3		T10	1		T5	1196
valid_sources[0x78]	15037	1			T3	11		T10	1		T5	1176
valid_sources[0x79]	14775	1			T3	3		T5	1202		T11	426
valid_sources[0x7a]	47731	1			T1	1		T3	1		T10	2
valid_sources[0x7b]	13520	1			T10	10		T5	1141		T11	469
valid_sources[0x7c]	12613	1			T3	7		T10	1		T5	1147
valid_sources[0x7d]	13815	1			T3	2		T10	4		T5	1199
valid_sources[0x7e]	64859	1			T1	3		T10	1		T5	1164
valid_sources[0x7f]	15835	1			T3	3		T10	3		T5	1192
valid_sources[0x80]	16242	1			T1	1		T10	2		T5	1181

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1907534

1

T1

87

T3

86

T10

101

values[0x0]

all_enables

biggest_size

144618

1

T1

53

T3

83

T10

98

values[0x1]

all_enables

biggest_size

144135

1

T1

54

T3

76

T10

78