Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	99532226	14555	0	0
claim_transition_if_regwen_rd_A	99532226	1472	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99532226	14555	0	0
T5	388026	13	0	0
T6	11698	0	0	0
T7	94468	0	0	0
T11	207177	15	0	0
T12	32121	0	0	0
T13	29300	0	0	0
T15	0	5	0	0
T18	6634	0	0	0
T27	947	0	0	0
T28	934	0	0	0
T29	1444	0	0	0
T40	0	11	0	0
T50	0	3	0	0
T77	0	1	0	0
T82	0	1	0	0
T126	0	16	0	0
T127	0	9	0	0
T128	0	1	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99532226	1472	0	0
T22	34068	0	0	0
T37	436537	0	0	0
T50	0	4	0	0
T82	503755	3	0	0
T84	25405	0	0	0
T85	22028	0	0	0
T86	878	0	0	0
T87	34564	0	0	0
T88	50316	0	0	0
T89	18799	0	0	0
T90	44170	0	0	0
T93	0	39	0	0
T95	0	8	0	0
T99	0	46	0	0
T125	0	206	0	0
T129	0	4	0	0
T130	0	41	0	0
T131	0	9	0	0
T132	0	5	0	0