Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

108427181

1

T1

7052

T2

33696

T3

51004

auto[1]

1396800

1

T1

297

T2

196

T9

1485

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

108449860

1

T1

7151

T2

33500

T3

51004

auto[1]

1374121

1

T1

198

T2

392

T9

1485

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7239762	1			T1	1234		T2	1670		T3	9838
auto[IdleSt]	23073564	1			T1	1497		T2	7673		T3	3117
auto[ClkMuxSt]	38081	1			T1	6		T2	4		T3	95
auto[CntIncrSt]	37750	1			T1	6		T2	4		T3	95
auto[CntProgSt]	1443240	1			T1	70		T2	8		T3	190
auto[TransCheckSt]	29274	1			T1	6		T2	4		T3	95
auto[TokenHashSt]	46909234	1			T1	322		T2	88		T3	22691
auto[FlashRmaSt]	30121	1			T1	6		T2	4		T3	85
auto[TokenCheck0St]	13461	1			T1	6		T2	4		T3	28
auto[TokenCheck1St]	9953	1			T1	6		T2	4		T3	8
auto[TransProgSt]	352236	1			T1	116		T2	8		T9	2078
auto[PostTransSt]	13692037	1			T1	1928		T2	7763		T3	14762
auto[ScrapSt]	136305	1			T40	8		T17	9		T20	1117
auto[EscalateSt]	6491773	1			T1	1289		T2	8713		T9	4099
auto[InvalidSt]	10325345	1			T1	856		T2	7944		T9	2323

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1845	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10325345	1			T1	856		T2	7944		T9	2323
EscalateSt	6491773	1			T1	1289		T2	8713		T9	4099
ScrapSt	136305	1			T40	8		T17	9		T20	1117
PostTransSt	13692037	1			T1	1928		T2	7763		T3	14762
TransProgSt	352236	1			T1	116		T2	8		T9	2078
TokenCheck1St	9953	1			T1	6		T2	4		T3	8
TokenCheck0St	13461	1			T1	6		T2	4		T3	28
FlashRmaSt	30121	1			T1	6		T2	4		T3	85
TokenHashSt	46909234	1			T1	322		T2	88		T3	22691
TransCheckSt	29274	1			T1	6		T2	4		T3	95
CntProgSt	1443240	1			T1	70		T2	8		T3	190
CntIncrSt	37750	1			T1	6		T2	4		T3	95
ClkMuxSt	38081	1			T1	6		T2	4		T3	95
IdleSt	23073564	1			T1	1497		T2	7673		T3	3117
ResetSt	7239762	1			T1	1234		T2	1670		T3	9838
arcs[ResetSt=>IdleSt]	55959	1			T1	12		T2	12		T3	96
arcs[IdleSt=>ScrapSt]	297	1			T40	1		T17	3		T20	1
arcs[IdleSt=>ClkMuxSt]	37814	1			T1	6		T2	4		T3	95
arcs[ClkMuxSt=>CntIncrSt]	37750	1			T1	6		T2	4		T3	95
arcs[CntIncrSt=>PostTransSt]	2092	1			T10	13		T4	26		T13	12
arcs[CntIncrSt=>CntProgSt]	35608	1			T1	6		T2	4		T3	95
arcs[CntProgSt=>PostTransSt]	5362	1			T9	13		T10	11		T4	35
arcs[CntProgSt=>TransCheckSt]	29274	1			T1	6		T2	4		T3	95
arcs[TransCheckSt=>PostTransSt]	3924	1			T3	52		T10	13		T4	38
arcs[TransCheckSt=>TokenHashSt]	25198	1			T1	6		T2	4		T3	43
arcs[TokenHashSt=>PostTransSt]	10914	1			T3	15		T9	9		T10	25
arcs[TokenHashSt=>FlashRmaSt]	13551	1			T1	6		T2	4		T3	28
arcs[FlashRmaSt=>TokenCheck0St]	13461	1			T1	6		T2	4		T3	28
arcs[TokenCheck0St=>PostTransSt]	3483	1			T3	20		T9	10		T10	9
arcs[TokenCheck0St=>TokenCheck1St]	9953	1			T1	6		T2	4		T3	8
arcs[TokenCheck1St=>PostTransSt]	706	1			T3	8		T4	2		T11	1
arcs[TransProgSt=>PostTransSt]	8452	1			T1	6		T2	4		T9	25
arcs[IdleSt=>EscalateSt]	207	1			T17	7		T50	5		T47	6
arcs[ClkMuxSt=>EscalateSt]	64	1			T17	1		T47	4		T48	4
arcs[CntIncrSt=>EscalateSt]	50	1			T17	1		T47	1		T49	2
arcs[CntProgSt=>EscalateSt]	972	1			T17	12		T50	9		T47	16
arcs[TransCheckSt=>EscalateSt]	152	1			T17	5		T50	7		T47	5
arcs[TokenHashSt=>EscalateSt]	733	1			T17	32		T41	1		T50	19
arcs[FlashRmaSt=>EscalateSt]	90	1			T17	4		T50	1		T47	2
arcs[TokenCheck0St=>EscalateSt]	25	1			T17	2		T50	1		T47	1
arcs[TokenCheck1St=>EscalateSt]	126	1			T17	3		T47	1		T49	8
arcs[TransProgSt=>EscalateSt]	669	1			T17	9		T50	7		T47	8
arcs[PostTransSt=>EscalateSt]	5652	1			T9	13		T10	11		T4	35
arcs[InvalidSt=>EscalateSt]	13467	1			T1	5		T2	6		T9	17

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7239611	1			T1	1234		T2	1670		T3	9838
auto[0]	auto[IdleSt]	23073418	1			T1	1497		T2	7673		T3	3117
auto[0]	auto[ClkMuxSt]	38034	1			T1	6		T2	4		T3	95
auto[0]	auto[CntIncrSt]	37710	1			T1	6		T2	4		T3	95
auto[0]	auto[CntProgSt]	1442571	1			T1	70		T2	8		T3	190
auto[0]	auto[TransCheckSt]	29180	1			T1	6		T2	4		T3	95
auto[0]	auto[TokenHashSt]	46908732	1			T1	322		T2	88		T3	22691
auto[0]	auto[FlashRmaSt]	30053	1			T1	6		T2	4		T3	85
auto[0]	auto[TokenCheck0St]	13441	1			T1	6		T2	4		T3	28
auto[0]	auto[TokenCheck1St]	9874	1			T1	6		T2	4		T3	8
auto[0]	auto[TransProgSt]	351777	1			T1	116		T2	8		T9	2078
auto[0]	auto[PostTransSt]	13689171	1			T1	1928		T2	7763		T3	14762
auto[0]	auto[ScrapSt]	136252	1			T40	8		T17	7		T20	1117
auto[0]	auto[EscalateSt]	5106951	1			T1	995		T2	8519		T9	2629
auto[0]	auto[InvalidSt]	10318561	1			T1	853		T2	7942		T9	2313
auto[1]	auto[ResetSt]	151	1			T17	3		T50	8		T47	1
auto[1]	auto[IdleSt]	146	1			T17	5		T50	3		T47	5
auto[1]	auto[ClkMuxSt]	47	1			T17	1		T47	3		T48	4
auto[1]	auto[CntIncrSt]	40	1			T17	1		T47	1		T49	1
auto[1]	auto[CntProgSt]	669	1			T17	11		T50	6		T47	13
auto[1]	auto[TransCheckSt]	94	1			T17	3		T50	4		T47	3
auto[1]	auto[TokenHashSt]	502	1			T17	27		T50	13		T47	9
auto[1]	auto[FlashRmaSt]	68	1			T17	4		T50	1		T47	2
auto[1]	auto[TokenCheck0St]	20	1			T17	2		T47	1		T226	1
auto[1]	auto[TokenCheck1St]	79	1			T17	2		T47	1		T49	4
auto[1]	auto[TransProgSt]	459	1			T17	5		T50	6		T47	5
auto[1]	auto[PostTransSt]	2866	1			T9	5		T10	6		T4	19
auto[1]	auto[ScrapSt]	53	1			T17	2		T47	1		T49	2
auto[1]	auto[EscalateSt]	1384822	1			T1	294		T2	194		T9	1470
auto[1]	auto[InvalidSt]	6784	1			T1	3		T2	2		T9	10

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7239612	1			T1	1234		T2	1670		T3	9838
auto[0]	auto[IdleSt]	23073426	1			T1	1497		T2	7673		T3	3117
auto[0]	auto[ClkMuxSt]	38042	1			T1	6		T2	4		T3	95
auto[0]	auto[CntIncrSt]	37719	1			T1	6		T2	4		T3	95
auto[0]	auto[CntProgSt]	1442593	1			T1	70		T2	8		T3	190
auto[0]	auto[TransCheckSt]	29180	1			T1	6		T2	4		T3	95
auto[0]	auto[TokenHashSt]	46908756	1			T1	322		T2	88		T3	22691
auto[0]	auto[FlashRmaSt]	30058	1			T1	6		T2	4		T3	85
auto[0]	auto[TokenCheck0St]	13442	1			T1	6		T2	4		T3	28
auto[0]	auto[TokenCheck1St]	9863	1			T1	6		T2	4		T3	8
auto[0]	auto[TransProgSt]	351794	1			T1	116		T2	8		T9	2078
auto[0]	auto[PostTransSt]	13689160	1			T1	1928		T2	7763		T3	14762
auto[0]	auto[ScrapSt]	136260	1			T40	8		T17	7		T20	1117
auto[0]	auto[EscalateSt]	5129448	1			T1	1093		T2	8325		T9	2629
auto[0]	auto[InvalidSt]	10318662	1			T1	854		T2	7940		T9	2316
auto[1]	auto[ResetSt]	150	1			T17	5		T50	7		T47	2
auto[1]	auto[IdleSt]	138	1			T17	3		T50	3		T47	3
auto[1]	auto[ClkMuxSt]	39	1			T17	1		T47	2		T48	4
auto[1]	auto[CntIncrSt]	31	1			T47	1		T49	2		T48	2
auto[1]	auto[CntProgSt]	647	1			T17	10		T50	5		T47	10
auto[1]	auto[TransCheckSt]	94	1			T17	2		T50	4		T47	2
auto[1]	auto[TokenHashSt]	478	1			T17	18		T41	1		T50	13
auto[1]	auto[FlashRmaSt]	63	1			T17	3		T50	1		T47	2
auto[1]	auto[TokenCheck0St]	19	1			T17	1		T50	1		T47	1
auto[1]	auto[TokenCheck1St]	90	1			T17	2		T49	6		T103	3
auto[1]	auto[TransProgSt]	442	1			T17	6		T50	4		T47	4
auto[1]	auto[PostTransSt]	2877	1			T9	8		T10	5		T4	16
auto[1]	auto[ScrapSt]	45	1			T17	2		T50	1		T48	2
auto[1]	auto[EscalateSt]	1362325	1			T1	196		T2	388		T9	1470
auto[1]	auto[InvalidSt]	6683	1			T1	2		T2	4		T9	7