Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1765090	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1993837

1

T1

652

T2

222

T3

409

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3398846	1			T1	527		T2	192		T3	353
values[0x0]	179710	1			T1	272		T2	90		T3	160
values[0x1]	180371	1			T1	232		T2	70		T3	152

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1401407	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2357520

1

T1

740

T2

246

T3

485

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12596	1			T1	1		T2	4		T4	2
valid_sources[0x01]	11888	1			T1	5		T3	3		T4	1
valid_sources[0x02]	13004	1			T1	1		T2	1		T3	3
valid_sources[0x03]	153508	1			T1	5		T2	1		T3	3
valid_sources[0x04]	14522	1			T1	4		T2	1		T4	1
valid_sources[0x05]	12367	1			T1	3		T2	4		T3	1
valid_sources[0x06]	11767	1			T1	4		T2	1		T5	62
valid_sources[0x07]	13553	1			T1	2		T2	1		T3	2
valid_sources[0x08]	15262	1			T3	2		T10	17		T5	52
valid_sources[0x09]	15345	1			T1	4		T3	3		T5	64
valid_sources[0x0a]	14638	1			T2	1		T13	1		T5	59
valid_sources[0x0b]	15502	1			T1	1		T3	5		T4	1
valid_sources[0x0c]	12362	1			T1	4		T3	2		T4	1
valid_sources[0x0d]	13070	1			T2	1		T3	5		T4	1
valid_sources[0x0e]	12819	1			T1	6		T2	1		T3	1
valid_sources[0x0f]	50309	1			T1	15		T2	1		T3	3
valid_sources[0x10]	13004	1			T1	3		T2	3		T4	2
valid_sources[0x11]	12326	1			T1	5		T2	1		T3	2
valid_sources[0x12]	21103	1			T1	6		T2	3		T3	4
valid_sources[0x13]	13713	1			T1	11		T2	2		T3	2
valid_sources[0x14]	14344	1			T1	4		T2	1		T3	1
valid_sources[0x15]	13018	1			T1	3		T2	2		T3	2
valid_sources[0x16]	14495	1			T1	15		T4	1		T5	45
valid_sources[0x17]	12337	1			T1	3		T2	3		T3	1
valid_sources[0x18]	26205	1			T1	4		T2	2		T3	5
valid_sources[0x19]	14615	1			T1	2		T3	2		T4	1
valid_sources[0x1a]	12631	1			T1	5		T2	2		T3	4
valid_sources[0x1b]	14372	1			T1	6		T2	1		T5	53
valid_sources[0x1c]	12356	1			T1	13		T3	6		T13	1
valid_sources[0x1d]	11950	1			T1	2		T2	1		T3	3
valid_sources[0x1e]	14102	1			T1	3		T2	1		T3	3
valid_sources[0x1f]	12007	1			T1	3		T2	1		T3	1
valid_sources[0x20]	12669	1			T1	3		T2	1		T4	1
valid_sources[0x21]	12791	1			T1	1		T2	5		T3	8
valid_sources[0x22]	12129	1			T1	1		T2	1		T3	1
valid_sources[0x23]	12106	1			T1	7		T2	1		T3	3
valid_sources[0x24]	11531	1			T1	5		T3	7		T4	1
valid_sources[0x25]	95104	1			T1	3		T2	1		T3	7
valid_sources[0x26]	13866	1			T1	2		T2	1		T3	1
valid_sources[0x27]	12024	1			T1	12		T2	3		T3	6
valid_sources[0x28]	12383	1			T1	1		T2	2		T3	5
valid_sources[0x29]	12726	1			T2	2		T3	1		T10	17
valid_sources[0x2a]	13559	1			T1	1		T3	1		T13	1
valid_sources[0x2b]	12906	1			T1	9		T4	1		T5	64
valid_sources[0x2c]	14707	1			T1	1		T2	1		T3	4
valid_sources[0x2d]	13210	1			T2	3		T5	55		T17	4
valid_sources[0x2e]	13142	1			T1	3		T3	4		T4	1
valid_sources[0x2f]	12549	1			T1	8		T2	1		T3	6
valid_sources[0x30]	13276	1			T1	1		T2	4		T4	2
valid_sources[0x31]	12802	1			T1	9		T2	4		T3	3
valid_sources[0x32]	13768	1			T1	5		T2	2		T3	4
valid_sources[0x33]	13605	1			T1	6		T2	2		T3	3
valid_sources[0x34]	12312	1			T1	5		T3	1		T5	55
valid_sources[0x35]	14888	1			T1	6		T3	2		T4	1
valid_sources[0x36]	13626	1			T1	9		T2	4		T3	4
valid_sources[0x37]	12768	1			T1	4		T2	1		T3	5
valid_sources[0x38]	12599	1			T1	9		T3	5		T4	1
valid_sources[0x39]	13269	1			T1	6		T2	2		T3	5
valid_sources[0x3a]	14028	1			T2	2		T3	3		T5	57
valid_sources[0x3b]	11883	1			T2	1		T3	1		T5	52
valid_sources[0x3c]	12236	1			T1	3		T2	2		T5	53
valid_sources[0x3d]	12976	1			T1	2		T2	2		T3	2
valid_sources[0x3e]	13511	1			T1	2		T2	2		T3	6
valid_sources[0x3f]	16382	1			T1	1		T4	1		T5	52
valid_sources[0x40]	12813	1			T1	1		T2	2		T3	6
valid_sources[0x41]	14432	1			T1	5		T2	1		T3	2
valid_sources[0x42]	15566	1			T1	2		T3	4		T13	2
valid_sources[0x43]	12745	1			T1	3		T5	54		T17	10
valid_sources[0x44]	12061	1			T1	4		T2	3		T3	6
valid_sources[0x45]	11827	1			T1	6		T4	3		T12	1
valid_sources[0x46]	12222	1			T1	3		T3	4		T5	63
valid_sources[0x47]	12883	1			T1	15		T2	1		T3	3
valid_sources[0x48]	12449	1			T1	5		T3	10		T4	2
valid_sources[0x49]	13205	1			T3	1		T4	3		T5	67
valid_sources[0x4a]	12452	1			T1	4		T5	48		T19	1
valid_sources[0x4b]	12500	1			T1	4		T2	2		T3	3
valid_sources[0x4c]	27366	1			T1	1		T2	2		T3	1
valid_sources[0x4d]	13105	1			T1	10		T2	1		T3	1
valid_sources[0x4e]	12051	1			T1	4		T2	1		T3	2
valid_sources[0x4f]	12185	1			T2	3		T3	1		T5	62
valid_sources[0x50]	14170	1			T1	8		T3	1		T13	3
valid_sources[0x51]	93814	1			T2	1		T3	1		T4	4
valid_sources[0x52]	14050	1			T1	5		T4	2		T5	64
valid_sources[0x53]	11842	1			T1	8		T2	3		T4	1
valid_sources[0x54]	13580	1			T1	1		T2	3		T5	53
valid_sources[0x55]	12848	1			T1	4		T3	4		T4	1
valid_sources[0x56]	12543	1			T1	2		T2	2		T3	3
valid_sources[0x57]	13078	1			T1	5		T3	5		T5	68
valid_sources[0x58]	13533	1			T1	7		T3	2		T5	58
valid_sources[0x59]	12378	1			T1	2		T3	3		T4	2
valid_sources[0x5a]	12053	1			T1	1		T3	3		T5	72
valid_sources[0x5b]	13079	1			T2	3		T5	42		T17	8
valid_sources[0x5c]	12285	1			T2	2		T3	3		T5	38
valid_sources[0x5d]	12434	1			T1	2		T2	1		T3	3
valid_sources[0x5e]	11941	1			T1	5		T2	2		T13	1
valid_sources[0x5f]	13095	1			T1	5		T2	1		T3	5
valid_sources[0x60]	12031	1			T1	5		T3	2		T4	1
valid_sources[0x61]	12598	1			T1	1		T2	2		T3	8
valid_sources[0x62]	13786	1			T2	1		T4	1		T5	59
valid_sources[0x63]	13465	1			T1	6		T3	1		T4	2
valid_sources[0x64]	12322	1			T1	2		T2	1		T3	2
valid_sources[0x65]	12611	1			T3	1		T4	1		T5	52
valid_sources[0x66]	12618	1			T2	1		T3	3		T4	2
valid_sources[0x67]	16552	1			T1	8		T2	3		T5	49
valid_sources[0x68]	12865	1			T1	8		T3	2		T4	2
valid_sources[0x69]	12880	1			T2	2		T3	2		T4	1
valid_sources[0x6a]	12659	1			T3	5		T4	2		T5	37
valid_sources[0x6b]	12037	1			T1	10		T3	12		T13	3
valid_sources[0x6c]	12910	1			T2	1		T3	8		T5	57
valid_sources[0x6d]	12025	1			T1	7		T2	3		T3	1
valid_sources[0x6e]	13686	1			T1	13		T2	3		T3	4
valid_sources[0x6f]	12557	1			T1	18		T2	2		T3	3
valid_sources[0x70]	13050	1			T1	5		T4	2		T10	17
valid_sources[0x71]	12540	1			T1	6		T2	2		T3	8
valid_sources[0x72]	12182	1			T1	3		T2	2		T3	5
valid_sources[0x73]	12104	1			T1	1		T2	2		T3	1
valid_sources[0x74]	13344	1			T1	3		T2	1		T4	1
valid_sources[0x75]	12086	1			T1	1		T2	2		T3	7
valid_sources[0x76]	12071	1			T2	2		T3	1		T10	17
valid_sources[0x77]	12912	1			T1	1		T2	1		T3	1
valid_sources[0x78]	12172	1			T1	1		T2	3		T3	2
valid_sources[0x79]	14662	1			T1	2		T3	3		T5	40
valid_sources[0x7a]	13212	1			T1	6		T3	3		T5	60
valid_sources[0x7b]	15700	1			T1	4		T2	1		T3	3
valid_sources[0x7c]	12001	1			T1	4		T2	2		T3	2
valid_sources[0x7d]	12203	1			T1	6		T2	2		T3	8
valid_sources[0x7e]	12617	1			T1	6		T2	1		T3	1
valid_sources[0x7f]	12287	1			T1	2		T2	1		T3	5
valid_sources[0x80]	12531	1			T4	1		T5	65		T17	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1683412

1

T1

221

T2

85

T3

135

values[0x0]

all_enables

biggest_size

155820

1

T1

234

T2

73

T3

137

values[0x1]

all_enables

biggest_size

154605

1

T1

197

T2

64

T3

137