Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	114903062	16901	0	0
claim_transition_if_regwen_rd_A	114903062	1584	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114903062	16901	0	0
T5	123108	3	0	0
T6	110665	0	0	0
T17	47270	0	0	0
T18	1424	0	0	0
T19	50177	0	0	0
T20	0	12	0	0
T22	16218	0	0	0
T27	1279	0	0	0
T35	9022	0	0	0
T37	0	6	0	0
T40	0	4	0	0
T62	3641	0	0	0
T63	4511	0	0	0
T86	0	2	0	0
T135	0	1	0	0
T136	0	11	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	9	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114903062	1584	0	0
T37	0	14	0	0
T40	673391	0	0	0
T66	0	13	0	0
T86	170901	2	0	0
T88	1889	0	0	0
T89	5883	0	0	0
T90	1213	0	0	0
T91	14893	0	0	0
T92	4981	0	0	0
T93	7444	0	0	0
T94	33884	0	0	0
T95	1473	0	0	0
T108	0	33	0	0
T109	0	31	0	0
T110	0	76	0	0
T123	0	99	0	0
T135	0	5	0	0
T140	0	14	0	0
T141	0	1	0	0