Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1327915	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1535088

1

T1

794

T2

180

T3

287

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2541538	1			T1	550		T2	138		T3	287
values[0x0]	160596	1			T1	298		T2	61		T3	92
values[0x1]	160869	1			T1	294		T2	67		T3	92

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1054416	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1808587

1

T1

884

T2

197

T3

335

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11572	1			T1	2		T2	2		T3	1
valid_sources[0x01]	9379	1			T2	1		T3	3		T5	23
valid_sources[0x02]	9550	1			T1	4		T2	2		T3	1
valid_sources[0x03]	8913	1			T1	1		T2	1		T3	3
valid_sources[0x04]	9858	1			T1	2		T2	2		T5	15
valid_sources[0x05]	9589	1			T1	5		T3	1		T5	15
valid_sources[0x06]	9335	1			T1	5		T3	1		T5	13
valid_sources[0x07]	9132	1			T1	9		T3	3		T5	10
valid_sources[0x08]	11200	1			T1	3		T2	2		T3	2
valid_sources[0x09]	8813	1			T1	6		T2	2		T3	2
valid_sources[0x0a]	9438	1			T1	6		T3	2		T5	18
valid_sources[0x0b]	10185	1			T1	7		T2	1		T5	17
valid_sources[0x0c]	9527	1			T1	2		T2	1		T5	20
valid_sources[0x0d]	9004	1			T1	6		T3	2		T5	15
valid_sources[0x0e]	8751	1			T2	3		T3	1		T5	9
valid_sources[0x0f]	9031	1			T2	2		T5	11		T11	1
valid_sources[0x10]	9487	1			T1	7		T5	19		T11	2
valid_sources[0x11]	15859	1			T1	2		T2	2		T5	19
valid_sources[0x12]	10030	1			T1	5		T3	1		T5	15
valid_sources[0x13]	9035	1			T1	9		T2	2		T3	3
valid_sources[0x14]	9458	1			T2	1		T3	2		T5	9
valid_sources[0x15]	8845	1			T1	10		T5	16		T11	4
valid_sources[0x16]	10685	1			T1	2		T5	13		T11	5
valid_sources[0x17]	9127	1			T3	1		T5	11		T11	1
valid_sources[0x18]	8884	1			T1	1		T2	2		T5	13
valid_sources[0x19]	9477	1			T2	4		T5	22		T11	4
valid_sources[0x1a]	10627	1			T1	1		T2	2		T3	4
valid_sources[0x1b]	11776	1			T1	5		T2	1		T3	3
valid_sources[0x1c]	9051	1			T1	2		T2	2		T3	1
valid_sources[0x1d]	58226	1			T1	10		T2	2		T3	1
valid_sources[0x1e]	9298	1			T1	7		T2	1		T3	5
valid_sources[0x1f]	9433	1			T1	8		T2	1		T3	3
valid_sources[0x20]	12664	1			T1	20		T2	1		T3	1
valid_sources[0x21]	14913	1			T1	6		T3	2		T5	10
valid_sources[0x22]	9822	1			T1	1		T2	1		T3	2
valid_sources[0x23]	9397	1			T1	2		T2	1		T3	3
valid_sources[0x24]	9176	1			T3	3		T4	10		T5	13
valid_sources[0x25]	9468	1			T1	6		T2	3		T3	2
valid_sources[0x26]	11256	1			T1	3		T5	25		T11	2
valid_sources[0x27]	8866	1			T1	5		T2	2		T4	2
valid_sources[0x28]	10404	1			T1	4		T2	1		T3	2
valid_sources[0x29]	9190	1			T1	2		T2	2		T3	2
valid_sources[0x2a]	9487	1			T1	4		T2	2		T3	2
valid_sources[0x2b]	9722	1			T5	21		T11	3		T6	253
valid_sources[0x2c]	9156	1			T1	3		T2	1		T3	2
valid_sources[0x2d]	13949	1			T1	8		T2	2		T3	2
valid_sources[0x2e]	9623	1			T1	5		T3	2		T4	7
valid_sources[0x2f]	9294	1			T1	3		T2	1		T3	3
valid_sources[0x30]	8849	1			T1	3		T2	1		T3	1
valid_sources[0x31]	9867	1			T1	5		T2	3		T3	1
valid_sources[0x32]	10577	1			T1	10		T3	2		T4	1
valid_sources[0x33]	9846	1			T1	4		T2	1		T3	2
valid_sources[0x34]	9291	1			T1	8		T2	1		T5	16
valid_sources[0x35]	9423	1			T1	4		T2	1		T3	1
valid_sources[0x36]	9141	1			T1	3		T2	1		T3	1
valid_sources[0x37]	9414	1			T1	7		T3	2		T5	9
valid_sources[0x38]	10596	1			T1	10		T2	1		T5	8
valid_sources[0x39]	10181	1			T1	1		T2	1		T3	1
valid_sources[0x3a]	9040	1			T1	5		T5	10		T11	5
valid_sources[0x3b]	9599	1			T1	1		T3	9		T5	12
valid_sources[0x3c]	9014	1			T1	5		T2	2		T5	13
valid_sources[0x3d]	20925	1			T1	6		T2	1		T3	3
valid_sources[0x3e]	9316	1			T2	1		T3	2		T5	16
valid_sources[0x3f]	16022	1			T1	3		T4	29		T5	10
valid_sources[0x40]	9579	1			T1	2		T2	3		T3	1
valid_sources[0x41]	9465	1			T1	13		T3	1		T5	9
valid_sources[0x42]	12476	1			T1	3		T2	1		T3	3
valid_sources[0x43]	11480	1			T1	4		T2	3		T3	4
valid_sources[0x44]	9713	1			T1	6		T2	2		T3	3
valid_sources[0x45]	8941	1			T1	3		T2	2		T3	3
valid_sources[0x46]	9847	1			T1	3		T5	18		T6	207
valid_sources[0x47]	11724	1			T1	2		T3	1		T4	3
valid_sources[0x48]	10331	1			T1	1		T2	1		T3	7
valid_sources[0x49]	9539	1			T1	8		T3	1		T5	11
valid_sources[0x4a]	9420	1			T1	12		T2	3		T4	20
valid_sources[0x4b]	34427	1			T1	1		T3	6		T5	12
valid_sources[0x4c]	8949	1			T1	7		T2	1		T3	4
valid_sources[0x4d]	9755	1			T1	3		T2	1		T4	3
valid_sources[0x4e]	11058	1			T5	12		T11	3		T6	226
valid_sources[0x4f]	15223	1			T1	3		T5	13		T11	2
valid_sources[0x50]	8874	1			T1	1		T2	3		T3	5
valid_sources[0x51]	9485	1			T1	13		T2	2		T3	1
valid_sources[0x52]	8471	1			T1	1		T2	3		T5	17
valid_sources[0x53]	9342	1			T1	1		T3	8		T4	15
valid_sources[0x54]	10947	1			T4	28		T5	12		T11	3
valid_sources[0x55]	9248	1			T2	1		T3	1		T5	10
valid_sources[0x56]	9422	1			T1	8		T2	1		T5	13
valid_sources[0x57]	10206	1			T1	9		T2	3		T3	4
valid_sources[0x58]	9521	1			T1	2		T2	1		T5	20
valid_sources[0x59]	8955	1			T1	4		T3	2		T5	13
valid_sources[0x5a]	9298	1			T3	2		T4	5		T5	8
valid_sources[0x5b]	9814	1			T1	5		T2	2		T5	9
valid_sources[0x5c]	9200	1			T1	6		T2	2		T3	4
valid_sources[0x5d]	8881	1			T1	5		T2	2		T3	4
valid_sources[0x5e]	9200	1			T1	8		T2	1		T3	4
valid_sources[0x5f]	9255	1			T2	1		T5	17		T11	4
valid_sources[0x60]	9188	1			T1	7		T2	1		T3	1
valid_sources[0x61]	9313	1			T1	2		T2	2		T3	3
valid_sources[0x62]	9272	1			T1	2		T2	1		T3	2
valid_sources[0x63]	9370	1			T1	15		T3	3		T4	8
valid_sources[0x64]	9448	1			T1	2		T2	2		T3	1
valid_sources[0x65]	9239	1			T1	4		T2	4		T5	13
valid_sources[0x66]	9213	1			T2	2		T3	3		T5	12
valid_sources[0x67]	10147	1			T1	7		T3	1		T4	13
valid_sources[0x68]	9244	1			T1	4		T3	5		T5	29
valid_sources[0x69]	10421	1			T3	6		T5	14		T11	4
valid_sources[0x6a]	10497	1			T1	2		T2	1		T3	2
valid_sources[0x6b]	9163	1			T1	4		T3	5		T5	6
valid_sources[0x6c]	9121	1			T1	4		T2	1		T3	2
valid_sources[0x6d]	9534	1			T1	7		T2	1		T3	2
valid_sources[0x6e]	9217	1			T1	1		T2	1		T3	1
valid_sources[0x6f]	9445	1			T1	2		T3	7		T5	6
valid_sources[0x70]	9093	1			T1	4		T2	1		T3	2
valid_sources[0x71]	10499	1			T1	6		T2	2		T3	3
valid_sources[0x72]	8912	1			T1	4		T3	2		T4	20
valid_sources[0x73]	9052	1			T1	8		T3	1		T5	12
valid_sources[0x74]	9131	1			T1	8		T2	1		T5	20
valid_sources[0x75]	12937	1			T1	1		T5	26		T11	2
valid_sources[0x76]	10340	1			T1	3		T3	1		T5	13
valid_sources[0x77]	9707	1			T1	3		T5	12		T6	206
valid_sources[0x78]	9488	1			T1	8		T2	1		T3	3
valid_sources[0x79]	9526	1			T1	1		T2	3		T3	1
valid_sources[0x7a]	9514	1			T3	2		T5	8		T11	1
valid_sources[0x7b]	9550	1			T1	3		T5	11		T6	236
valid_sources[0x7c]	10617	1			T1	4		T2	1		T5	13
valid_sources[0x7d]	10744	1			T1	3		T2	1		T3	5
valid_sources[0x7e]	31219	1			T1	6		T3	3		T5	10
valid_sources[0x7f]	9160	1			T1	5		T4	3		T5	14
valid_sources[0x80]	10447	1			T1	12		T2	2		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1258111

1

T1

279

T2

63

T3

130

values[0x0]

all_enables

biggest_size

139238

1

T1

265

T2

53

T3

82

values[0x1]

all_enables

biggest_size

137739

1

T1

250

T2

64

T3

75