Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	100.00	82.35	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	95516930	14423	0	0
claim_transition_if_regwen_rd_A	95516930	1718	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95516930	14423	0	0
T7	34111	0	0	0
T14	247220	1	0	0
T15	618388	0	0	0
T26	21110	0	0	0
T33	0	16	0	0
T38	0	8	0	0
T41	28597	0	0	0
T42	49221	0	0	0
T43	19949	0	0	0
T52	0	4	0	0
T57	0	5	0	0
T89	0	1	0	0
T157	869	0	0	0
T158	0	4	0	0
T159	0	5	0	0
T160	0	2	0	0
T161	0	11	0	0
T162	27341	0	0	0
T163	31722	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95516930	1718	0	0
T22	89999	0	0	0
T38	384427	0	0	0
T52	378821	1	0	0
T57	146393	0	0	0
T122	0	22	0	0
T129	0	17	0	0
T139	0	47	0	0
T158	0	12	0	0
T164	0	1	0	0
T165	0	2	0	0
T166	0	15	0	0
T167	0	5	0	0
T168	0	14	0	0
T169	4833	0	0	0
T170	28342	0	0	0
T171	28962	0	0	0
T172	40174	0	0	0
T173	6901	0	0	0
T174	217624	0	0	0