Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1520485	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1733844

1

T1

554

T2

14647

T3

3970

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2922422	1			T1	817		T2	28167		T3	6692
values[0x0]	166074	1			T1	79		T2	412		T3	355
values[0x1]	165833	1			T1	89		T2	431		T3	325

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1207547	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2046782

1

T1

639

T2

17553

T3

4662

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11757	1			T1	5		T12	2		T20	1
valid_sources[0x01]	12736	1			T1	4		T10	1		T12	1
valid_sources[0x02]	9512	1			T1	4		T20	3		T26	1
valid_sources[0x03]	9707	1			T11	2		T12	1		T20	1
valid_sources[0x04]	10252	1			T23	14		T22	11		T39	2
valid_sources[0x05]	10565	1			T1	6		T12	1		T23	21
valid_sources[0x06]	11077	1			T1	4		T11	2		T20	8
valid_sources[0x07]	9969	1			T1	4		T20	3		T23	20
valid_sources[0x08]	16190	1			T2	17		T11	3		T20	2
valid_sources[0x09]	10133	1			T1	12		T12	3		T20	1
valid_sources[0x0a]	11159	1			T10	1		T11	2		T20	2
valid_sources[0x0b]	9681	1			T1	4		T12	2		T23	7
valid_sources[0x0c]	35481	1			T11	3		T20	5		T26	1
valid_sources[0x0d]	10045	1			T20	1		T26	5		T23	13
valid_sources[0x0e]	10037	1			T20	7		T23	11		T22	6
valid_sources[0x0f]	12532	1			T1	23		T11	1		T20	2
valid_sources[0x10]	9951	1			T20	3		T23	19		T22	2
valid_sources[0x11]	12079	1			T1	6		T10	1		T11	5
valid_sources[0x12]	11536	1			T1	2		T20	1		T23	11
valid_sources[0x13]	93023	1			T10	1		T11	2		T20	1
valid_sources[0x14]	11602	1			T1	8		T10	1		T11	1
valid_sources[0x15]	11764	1			T1	8		T12	1		T20	2
valid_sources[0x16]	9487	1			T1	5		T20	2		T23	12
valid_sources[0x17]	10169	1			T10	1		T20	11		T26	4
valid_sources[0x18]	9704	1			T20	5		T26	2		T23	14
valid_sources[0x19]	13219	1			T1	6		T12	4		T20	1
valid_sources[0x1a]	9744	1			T10	1		T20	3		T23	14
valid_sources[0x1b]	10668	1			T1	1		T20	5		T26	3
valid_sources[0x1c]	9807	1			T12	3		T23	24		T22	32
valid_sources[0x1d]	86500	1			T10	1		T11	3		T14	350
valid_sources[0x1e]	9859	1			T1	7		T2	17		T10	1
valid_sources[0x1f]	12132	1			T1	2		T12	1		T20	4
valid_sources[0x20]	10095	1			T1	2		T10	1		T20	7
valid_sources[0x21]	10593	1			T1	4		T20	4		T23	15
valid_sources[0x22]	10310	1			T1	1		T12	1		T20	8
valid_sources[0x23]	11376	1			T1	2		T11	2		T20	1
valid_sources[0x24]	10123	1			T1	17		T12	1		T20	2
valid_sources[0x25]	11674	1			T1	2		T20	2		T26	3
valid_sources[0x26]	10070	1			T1	4		T10	1		T23	8
valid_sources[0x27]	10837	1			T10	1		T11	2		T20	6
valid_sources[0x28]	9896	1			T20	2		T23	18		T22	2
valid_sources[0x29]	11368	1			T1	2		T20	1		T23	17
valid_sources[0x2a]	9527	1			T11	1		T20	4		T23	24
valid_sources[0x2b]	11217	1			T1	1		T10	1		T20	4
valid_sources[0x2c]	10203	1			T12	1		T20	4		T26	2
valid_sources[0x2d]	10104	1			T1	3		T20	8		T23	19
valid_sources[0x2e]	10887	1			T1	1		T11	1		T20	2
valid_sources[0x2f]	10781	1			T11	1		T12	4		T20	5
valid_sources[0x30]	13602	1			T1	7		T23	16		T22	12
valid_sources[0x31]	9941	1			T12	1		T20	1		T23	13
valid_sources[0x32]	10018	1			T1	3		T23	27		T22	29
valid_sources[0x33]	10235	1			T10	1		T11	1		T26	1
valid_sources[0x34]	10356	1			T1	7		T20	7		T23	11
valid_sources[0x35]	10144	1			T20	9		T23	16		T6	7
valid_sources[0x36]	9850	1			T10	1		T12	1		T20	6
valid_sources[0x37]	10461	1			T2	17		T12	2		T23	22
valid_sources[0x38]	34657	1			T1	12		T11	1		T20	4
valid_sources[0x39]	127584	1			T10	1		T12	1		T20	9
valid_sources[0x3a]	11423	1			T1	7		T20	3		T26	5
valid_sources[0x3b]	9814	1			T20	6		T90	21		T23	12
valid_sources[0x3c]	10388	1			T20	3		T23	7		T6	2
valid_sources[0x3d]	9922	1			T26	3		T23	11		T22	20
valid_sources[0x3e]	11405	1			T1	11		T10	1		T26	1
valid_sources[0x3f]	12124	1			T1	1		T11	1		T20	3
valid_sources[0x40]	10098	1			T20	6		T26	1		T23	9
valid_sources[0x41]	9905	1			T12	3		T20	10		T26	1
valid_sources[0x42]	10328	1			T12	1		T20	2		T23	17
valid_sources[0x43]	9810	1			T1	2		T26	6		T23	18
valid_sources[0x44]	10145	1			T10	1		T20	2		T26	4
valid_sources[0x45]	9831	1			T20	6		T23	24		T22	27
valid_sources[0x46]	9943	1			T11	2		T20	1		T23	18
valid_sources[0x47]	9974	1			T1	2		T12	1		T20	3
valid_sources[0x48]	10317	1			T11	1		T20	8		T23	9
valid_sources[0x49]	9718	1			T1	17		T20	2		T26	3
valid_sources[0x4a]	10101	1			T2	17		T11	1		T20	1
valid_sources[0x4b]	9851	1			T1	1		T10	1		T20	1
valid_sources[0x4c]	9703	1			T10	1		T20	4		T26	3
valid_sources[0x4d]	10253	1			T12	1		T26	5		T23	12
valid_sources[0x4e]	12437	1			T11	1		T20	1		T26	4
valid_sources[0x4f]	12695	1			T11	1		T20	4		T26	1
valid_sources[0x50]	10373	1			T10	1		T11	1		T12	3
valid_sources[0x51]	11079	1			T1	20		T12	1		T26	10
valid_sources[0x52]	9949	1			T1	19		T20	2		T23	11
valid_sources[0x53]	10620	1			T1	3		T26	7		T23	14
valid_sources[0x54]	10027	1			T1	21		T20	5		T26	1
valid_sources[0x55]	12900	1			T1	3		T10	1		T12	3
valid_sources[0x56]	14107	1			T1	2		T10	1		T20	4
valid_sources[0x57]	38733	1			T1	7		T2	28891		T11	4
valid_sources[0x58]	9777	1			T1	7		T11	2		T26	1
valid_sources[0x59]	11237	1			T10	1		T11	1		T20	2
valid_sources[0x5a]	10047	1			T1	5		T20	8		T23	16
valid_sources[0x5b]	11424	1			T1	6		T10	1		T20	8
valid_sources[0x5c]	9892	1			T1	4		T10	1		T20	8
valid_sources[0x5d]	13904	1			T20	2		T23	15		T22	12
valid_sources[0x5e]	13466	1			T1	4		T12	1		T13	58
valid_sources[0x5f]	10259	1			T12	1		T20	2		T26	1
valid_sources[0x60]	9983	1			T1	2		T11	1		T12	2
valid_sources[0x61]	11689	1			T1	6		T12	1		T20	4
valid_sources[0x62]	9944	1			T1	1		T12	1		T20	2
valid_sources[0x63]	11711	1			T1	4		T23	8		T6	2
valid_sources[0x64]	10615	1			T1	1		T20	4		T23	11
valid_sources[0x65]	9678	1			T1	4		T23	19		T22	21
valid_sources[0x66]	9635	1			T20	2		T26	8		T23	22
valid_sources[0x67]	11685	1			T20	3		T23	12		T39	7
valid_sources[0x68]	9777	1			T1	8		T20	1		T26	2
valid_sources[0x69]	10131	1			T1	10		T12	1		T20	2
valid_sources[0x6a]	10587	1			T12	1		T20	3		T23	11
valid_sources[0x6b]	9775	1			T1	4		T2	17		T12	1
valid_sources[0x6c]	10185	1			T20	2		T26	1		T23	17
valid_sources[0x6d]	9493	1			T26	1		T23	19		T22	33
valid_sources[0x6e]	10183	1			T1	2		T12	4		T20	7
valid_sources[0x6f]	10068	1			T1	12		T20	1		T23	8
valid_sources[0x70]	10014	1			T10	1		T20	5		T26	6
valid_sources[0x71]	10356	1			T10	1		T20	5		T23	24
valid_sources[0x72]	14330	1			T20	5		T26	4		T23	12
valid_sources[0x73]	9850	1			T1	2		T10	1		T12	1
valid_sources[0x74]	9928	1			T26	2		T23	15		T39	7
valid_sources[0x75]	10506	1			T1	1		T12	1		T20	1
valid_sources[0x76]	10068	1			T10	1		T26	1		T23	10
valid_sources[0x77]	12768	1			T1	8		T11	1		T23	8
valid_sources[0x78]	10301	1			T1	3		T20	2		T23	21
valid_sources[0x79]	9406	1			T1	9		T12	1		T20	5
valid_sources[0x7a]	9520	1			T11	1		T12	3		T20	4
valid_sources[0x7b]	11836	1			T1	1		T10	1		T20	1
valid_sources[0x7c]	11160	1			T1	9		T26	2		T23	17
valid_sources[0x7d]	10401	1			T1	4		T12	3		T20	4
valid_sources[0x7e]	10108	1			T20	3		T26	1		T23	26
valid_sources[0x7f]	10201	1			T20	1		T23	9		T22	34
valid_sources[0x80]	14773	1			T1	14		T12	5		T20	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1447380

1

T1

409

T2

13923

T3

3392

values[0x0]

all_enables

biggest_size

144143

1

T1

63

T2

350

T3

301

values[0x1]

all_enables

biggest_size

142321

1

T1

82

T2

374

T3

277