Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	95226957	14146	0	0
claim_transition_if_regwen_rd_A	95226957	1532	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95226957	14146	0	0
T29	13695	0	0	0
T42	0	5	0	0
T44	169737	3	0	0
T45	221864	0	0	0
T46	0	1	0	0
T59	4490	0	0	0
T62	27705	0	0	0
T100	0	19	0	0
T101	0	2	0	0
T102	0	12	0	0
T140	0	4	0	0
T141	0	16	0	0
T142	0	6	0	0
T143	0	2	0	0
T144	2971	0	0	0
T145	24471	0	0	0
T146	21837	0	0	0
T147	1501	0	0	0
T148	130916	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95226957	1532	0	0
T32	8981	0	0	0
T42	303720	6	0	0
T47	0	2	0	0
T52	34908	0	0	0
T111	0	13	0	0
T121	0	12	0	0
T143	0	3	0	0
T149	0	4	0	0
T150	0	3	0	0
T151	0	38	0	0
T152	0	7	0	0
T153	0	47	0	0
T154	4165	0	0	0
T155	51397	0	0	0
T156	27633	0	0	0
T157	264908	0	0	0
T158	27321	0	0	0
T159	1793	0	0	0
T160	24967	0	0	0