Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1849775	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2076784

1

T1

240

T2

377

T3

1032

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3572963	1			T1	201		T2	522		T3	826
values[0x0]	176137	1			T1	96		T2	80		T3	353
values[0x1]	177459	1			T1	80		T2	72		T3	343

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1470646	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2455913

1

T1

275

T2

424

T3

1146

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11505	1			T1	2		T2	2		T11	5
valid_sources[0x01]	10752	1			T1	1		T2	2		T3	1
valid_sources[0x02]	9605	1			T3	28		T12	2		T13	25
valid_sources[0x03]	38695	1			T1	2		T2	2		T12	4
valid_sources[0x04]	36134	1			T11	1		T13	18		T14	1
valid_sources[0x05]	10014	1			T1	2		T2	1		T11	2
valid_sources[0x06]	80004	1			T1	1		T2	4		T11	3
valid_sources[0x07]	12606	1			T1	3		T2	4		T11	1
valid_sources[0x08]	10120	1			T1	1		T2	3		T11	2
valid_sources[0x09]	12538	1			T1	1		T2	2		T12	2
valid_sources[0x0a]	24653	1			T2	3		T11	2		T12	5
valid_sources[0x0b]	9281	1			T1	1		T2	3		T3	6
valid_sources[0x0c]	9464	1			T1	4		T2	4		T3	2
valid_sources[0x0d]	9825	1			T1	2		T2	3		T11	4
valid_sources[0x0e]	11180	1			T1	2		T2	4		T3	5
valid_sources[0x0f]	9888	1			T1	1		T2	6		T12	5
valid_sources[0x10]	9197	1			T1	1		T2	1		T11	3
valid_sources[0x11]	9603	1			T1	3		T2	2		T11	1
valid_sources[0x12]	9709	1			T2	1		T12	3		T13	11
valid_sources[0x13]	9321	1			T1	2		T3	8		T13	21
valid_sources[0x14]	89139	1			T1	2		T2	2		T12	5
valid_sources[0x15]	9655	1			T1	1		T2	1		T3	13
valid_sources[0x16]	11278	1			T2	1		T3	10		T11	3
valid_sources[0x17]	9824	1			T2	5		T3	24		T13	10
valid_sources[0x18]	23380	1			T1	5		T2	8		T11	5
valid_sources[0x19]	9855	1			T2	4		T11	3		T12	1
valid_sources[0x1a]	28763	1			T1	1		T2	1		T11	2
valid_sources[0x1b]	9542	1			T1	2		T2	3		T12	9
valid_sources[0x1c]	9688	1			T2	3		T3	8		T11	1
valid_sources[0x1d]	11583	1			T2	3		T12	15		T13	12
valid_sources[0x1e]	9897	1			T1	2		T2	1		T11	1
valid_sources[0x1f]	9984	1			T1	3		T11	3		T12	11
valid_sources[0x20]	9396	1			T1	3		T2	3		T3	29
valid_sources[0x21]	9999	1			T1	5		T2	3		T12	7
valid_sources[0x22]	18275	1			T1	3		T2	2		T3	21
valid_sources[0x23]	9822	1			T2	2		T11	3		T12	10
valid_sources[0x24]	10005	1			T2	6		T12	6		T13	17
valid_sources[0x25]	10157	1			T1	1		T2	4		T3	12
valid_sources[0x26]	9760	1			T1	1		T2	2		T3	24
valid_sources[0x27]	10061	1			T1	2		T2	2		T11	1
valid_sources[0x28]	10450	1			T1	2		T2	1		T11	5
valid_sources[0x29]	9847	1			T1	1		T2	6		T3	14
valid_sources[0x2a]	10065	1			T1	2		T2	3		T12	5
valid_sources[0x2b]	9907	1			T1	2		T2	4		T11	1
valid_sources[0x2c]	13454	1			T2	3		T11	3		T12	4
valid_sources[0x2d]	10083	1			T1	1		T2	5		T11	1
valid_sources[0x2e]	9740	1			T1	3		T2	1		T12	5
valid_sources[0x2f]	9594	1			T1	1		T2	2		T3	24
valid_sources[0x30]	11433	1			T1	2		T2	4		T3	9
valid_sources[0x31]	9225	1			T1	1		T2	2		T11	1
valid_sources[0x32]	10321	1			T1	2		T2	2		T11	1
valid_sources[0x33]	12866	1			T1	3		T2	5		T11	1
valid_sources[0x34]	9842	1			T1	2		T2	1		T11	1
valid_sources[0x35]	11607	1			T2	2		T11	1		T12	2
valid_sources[0x36]	9473	1			T2	2		T11	1		T12	2
valid_sources[0x37]	9531	1			T1	3		T2	1		T11	1
valid_sources[0x38]	28989	1			T2	1		T3	4		T11	4
valid_sources[0x39]	9822	1			T1	1		T2	1		T3	1
valid_sources[0x3a]	10156	1			T1	2		T2	2		T11	5
valid_sources[0x3b]	25406	1			T1	5		T2	7		T3	5
valid_sources[0x3c]	9653	1			T1	1		T2	3		T11	1
valid_sources[0x3d]	10713	1			T2	4		T3	7		T11	2
valid_sources[0x3e]	9822	1			T1	1		T2	2		T3	5
valid_sources[0x3f]	10201	1			T1	2		T2	2		T13	18
valid_sources[0x40]	9868	1			T2	3		T12	8		T13	6
valid_sources[0x41]	9743	1			T1	3		T2	2		T3	5
valid_sources[0x42]	9260	1			T1	3		T2	4		T11	1
valid_sources[0x43]	10052	1			T1	1		T2	4		T11	1
valid_sources[0x44]	9691	1			T2	2		T12	7		T13	13
valid_sources[0x45]	9417	1			T2	6		T11	1		T12	3
valid_sources[0x46]	16695	1			T2	3		T12	2		T13	6
valid_sources[0x47]	11186	1			T1	1		T2	4		T11	2
valid_sources[0x48]	10021	1			T2	3		T3	46		T11	1
valid_sources[0x49]	14563	1			T1	4		T13	20		T14	3
valid_sources[0x4a]	10102	1			T2	4		T11	1		T12	4
valid_sources[0x4b]	9803	1			T1	1		T2	3		T3	44
valid_sources[0x4c]	9878	1			T1	3		T2	4		T12	8
valid_sources[0x4d]	9577	1			T2	4		T12	7		T13	5
valid_sources[0x4e]	9418	1			T1	2		T2	1		T12	4
valid_sources[0x4f]	12963	1			T1	3		T3	66		T11	2
valid_sources[0x50]	9458	1			T2	4		T3	87		T12	8
valid_sources[0x51]	10496	1			T1	2		T2	6		T11	3
valid_sources[0x52]	13446	1			T1	1		T2	3		T11	2
valid_sources[0x53]	10935	1			T1	1		T2	1		T11	1
valid_sources[0x54]	9409	1			T2	3		T3	37		T11	1
valid_sources[0x55]	9714	1			T1	1		T2	1		T12	9
valid_sources[0x56]	9611	1			T1	2		T2	3		T11	3
valid_sources[0x57]	11263	1			T2	6		T12	13		T13	20
valid_sources[0x58]	9459	1			T2	6		T3	25		T11	1
valid_sources[0x59]	25355	1			T1	1		T2	2		T3	12
valid_sources[0x5a]	9824	1			T1	1		T2	2		T12	2
valid_sources[0x5b]	13896	1			T1	1		T3	12		T12	6
valid_sources[0x5c]	9422	1			T1	3		T2	2		T11	1
valid_sources[0x5d]	10980	1			T1	2		T2	2		T3	9
valid_sources[0x5e]	12424	1			T2	2		T11	1		T12	5
valid_sources[0x5f]	12601	1			T2	2		T3	11		T11	1
valid_sources[0x60]	9813	1			T1	2		T2	2		T11	2
valid_sources[0x61]	79819	1			T1	1		T2	7		T3	1
valid_sources[0x62]	9735	1			T1	1		T2	2		T11	2
valid_sources[0x63]	17709	1			T1	1		T2	3		T11	1
valid_sources[0x64]	11066	1			T2	5		T11	2		T12	7
valid_sources[0x65]	11087	1			T1	5		T3	9		T11	2
valid_sources[0x66]	9606	1			T2	5		T3	13		T11	2
valid_sources[0x67]	80005	1			T1	1		T2	4		T3	2
valid_sources[0x68]	10073	1			T1	2		T2	1		T12	4
valid_sources[0x69]	9729	1			T2	3		T3	2		T11	2
valid_sources[0x6a]	9961	1			T1	1		T2	3		T11	1
valid_sources[0x6b]	9582	1			T2	3		T3	22		T12	12
valid_sources[0x6c]	84489	1			T1	1		T2	1		T11	1
valid_sources[0x6d]	9304	1			T1	5		T12	7		T13	4
valid_sources[0x6e]	11679	1			T1	1		T2	2		T12	3
valid_sources[0x6f]	10557	1			T1	2		T2	2		T3	14
valid_sources[0x70]	9582	1			T1	3		T2	3		T11	2
valid_sources[0x71]	9550	1			T1	1		T2	2		T11	1
valid_sources[0x72]	13278	1			T1	2		T2	1		T3	3
valid_sources[0x73]	9688	1			T2	5		T11	1		T12	16
valid_sources[0x74]	12887	1			T2	3		T3	40		T13	13
valid_sources[0x75]	11366	1			T1	1		T3	40		T12	8
valid_sources[0x76]	9520	1			T1	3		T2	2		T11	4
valid_sources[0x77]	9513	1			T1	3		T2	2		T11	1
valid_sources[0x78]	9900	1			T1	1		T2	3		T3	2
valid_sources[0x79]	9820	1			T1	3		T2	5		T11	1
valid_sources[0x7a]	11154	1			T2	4		T12	2		T13	15
valid_sources[0x7b]	10912	1			T1	2		T2	2		T11	1
valid_sources[0x7c]	9604	1			T2	3		T12	4		T13	10
valid_sources[0x7d]	27734	1			T1	4		T2	5		T3	29
valid_sources[0x7e]	9942	1			T1	1		T2	2		T3	16
valid_sources[0x7f]	12827	1			T1	3		T2	2		T11	3
valid_sources[0x80]	9921	1			T1	2		T2	3		T12	22

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1771911

1

T1

85

T2

249

T3

431

values[0x0]

all_enables

biggest_size

152719

1

T1

84

T2

64

T3

310

values[0x1]

all_enables

biggest_size

152154

1

T1

71

T2

64

T3

291