Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	100.00	82.35	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	120493138	14148	0	0
claim_transition_if_regwen_rd_A	120493138	1310	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120493138	14148	0	0
T18	197102	2	0	0
T20	0	2	0	0
T25	170909	1	0	0
T28	26818	0	0	0
T37	8600	0	0	0
T38	3684	0	0	0
T39	45844	0	0	0
T40	5007	0	0	0
T41	30172	0	0	0
T42	0	17	0	0
T46	939803	0	0	0
T47	0	1	0	0
T82	1672	0	0	0
T86	0	7	0	0
T94	0	4	0	0
T96	0	2	0	0
T154	0	3	0	0
T155	0	17	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120493138	1310	0	0
T18	197102	4	0	0
T20	0	5	0	0
T25	170909	0	0	0
T28	26818	0	0	0
T37	8600	0	0	0
T38	3684	0	0	0
T39	45844	0	0	0
T40	5007	0	0	0
T41	30172	0	0	0
T46	939803	0	0	0
T47	0	5	0	0
T71	0	2	0	0
T82	1672	0	0	0
T156	0	10	0	0
T157	0	3	0	0
T158	0	3	0	0
T159	0	27	0	0
T160	0	51	0	0
T161	0	3	0	0