Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1338068	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1554922

1

T1

103

T2

625

T3

169

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2558047	1			T1	90		T2	516		T3	118
values[0x0]	166991	1			T1	35		T2	199		T3	74
values[0x1]	167952	1			T1	43		T2	225		T3	62

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1062014	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1830976

1

T1

118

T2

698

T3

187

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13752	1			T6	1		T25	2		T16	2
valid_sources[0x01]	10311	1			T3	8		T9	4		T25	3
valid_sources[0x02]	10803	1			T8	1		T16	5		T24	94
valid_sources[0x03]	8732	1			T25	3		T17	2		T24	81
valid_sources[0x04]	8808	1			T25	3		T17	2		T24	73
valid_sources[0x05]	8854	1			T2	13		T16	23		T17	2
valid_sources[0x06]	9808	1			T3	2		T25	1		T16	17
valid_sources[0x07]	8903	1			T9	4		T16	7		T17	1
valid_sources[0x08]	8710	1			T16	10		T17	5		T24	78
valid_sources[0x09]	8779	1			T25	4		T16	3		T17	3
valid_sources[0x0a]	9332	1			T16	1		T17	5		T24	82
valid_sources[0x0b]	8653	1			T2	10		T25	1		T16	2
valid_sources[0x0c]	8671	1			T3	4		T16	2		T24	100
valid_sources[0x0d]	8678	1			T3	1		T7	3		T16	11
valid_sources[0x0e]	10037	1			T25	11		T16	9		T17	1
valid_sources[0x0f]	20017	1			T9	2		T7	59		T16	7
valid_sources[0x10]	8848	1			T9	2		T25	1		T16	13
valid_sources[0x11]	8935	1			T2	45		T8	1		T9	2
valid_sources[0x12]	8589	1			T25	6		T16	14		T17	3
valid_sources[0x13]	29137	1			T7	8		T25	6		T17	1
valid_sources[0x14]	8755	1			T6	20		T25	1		T16	8
valid_sources[0x15]	8784	1			T2	33		T3	4		T25	2
valid_sources[0x16]	8700	1			T25	1		T16	2		T24	81
valid_sources[0x17]	8692	1			T2	6		T8	1		T16	16
valid_sources[0x18]	9029	1			T1	1		T9	4		T16	6
valid_sources[0x19]	10707	1			T25	1		T16	8		T24	91
valid_sources[0x1a]	11135	1			T3	3		T25	3		T16	2
valid_sources[0x1b]	12348	1			T2	17		T6	41		T7	2
valid_sources[0x1c]	8170	1			T9	6		T7	50		T25	1
valid_sources[0x1d]	11303	1			T16	1		T17	3		T24	102
valid_sources[0x1e]	9268	1			T17	1		T24	84		T80	4
valid_sources[0x1f]	8919	1			T25	12		T17	1		T24	80
valid_sources[0x20]	9699	1			T2	8		T17	2		T24	96
valid_sources[0x21]	14858	1			T2	6		T16	2		T24	81
valid_sources[0x22]	8924	1			T7	5		T25	17		T17	1
valid_sources[0x23]	8964	1			T2	4		T3	1		T24	94
valid_sources[0x24]	8514	1			T17	2		T24	104		T80	8
valid_sources[0x25]	11225	1			T2	15		T7	43		T25	3
valid_sources[0x26]	12102	1			T9	2		T24	89		T80	2
valid_sources[0x27]	11312	1			T8	1		T25	4		T17	1
valid_sources[0x28]	8652	1			T25	10		T16	1		T17	4
valid_sources[0x29]	11516	1			T25	2		T17	3		T24	79
valid_sources[0x2a]	8521	1			T25	2		T16	2		T17	2
valid_sources[0x2b]	9747	1			T16	4		T17	3		T24	77
valid_sources[0x2c]	9180	1			T3	5		T7	4		T25	9
valid_sources[0x2d]	11377	1			T3	18		T8	1		T16	13
valid_sources[0x2e]	8675	1			T16	21		T17	1		T24	84
valid_sources[0x2f]	9519	1			T6	5		T25	3		T16	3
valid_sources[0x30]	8878	1			T1	7		T25	4		T17	5
valid_sources[0x31]	9196	1			T8	1		T25	8		T16	3
valid_sources[0x32]	8840	1			T6	44		T16	3		T17	2
valid_sources[0x33]	8622	1			T1	5		T25	2		T16	9
valid_sources[0x34]	10353	1			T25	4		T17	1		T24	94
valid_sources[0x35]	8911	1			T3	7		T25	4		T17	3
valid_sources[0x36]	9325	1			T8	1		T9	4		T25	2
valid_sources[0x37]	8849	1			T2	24		T9	1		T16	3
valid_sources[0x38]	10306	1			T2	2		T9	9		T7	1
valid_sources[0x39]	8892	1			T25	1		T16	13		T24	74
valid_sources[0x3a]	10966	1			T1	70		T3	3		T16	1
valid_sources[0x3b]	8741	1			T25	3		T16	12		T24	99
valid_sources[0x3c]	8784	1			T3	1		T17	5		T24	86
valid_sources[0x3d]	9782	1			T8	1		T25	6		T16	11
valid_sources[0x3e]	35932	1			T16	2		T17	2		T24	98
valid_sources[0x3f]	9250	1			T9	1		T25	11		T16	5
valid_sources[0x40]	8680	1			T25	8		T16	7		T17	1
valid_sources[0x41]	11894	1			T8	1		T16	16		T17	1
valid_sources[0x42]	8885	1			T3	2		T6	48		T25	5
valid_sources[0x43]	8435	1			T2	29		T9	3		T16	9
valid_sources[0x44]	16542	1			T8	3		T16	7		T17	2
valid_sources[0x45]	10666	1			T2	79		T24	90		T80	1
valid_sources[0x46]	9266	1			T16	4		T24	101		T80	3
valid_sources[0x47]	10916	1			T16	20		T17	4		T24	89
valid_sources[0x48]	9399	1			T3	4		T25	8		T16	9
valid_sources[0x49]	11843	1			T16	4		T17	5		T24	70
valid_sources[0x4a]	9552	1			T3	14		T9	1		T17	1
valid_sources[0x4b]	10183	1			T2	27		T7	15		T16	13
valid_sources[0x4c]	8560	1			T3	6		T25	9		T16	10
valid_sources[0x4d]	13855	1			T2	22		T8	2		T7	1
valid_sources[0x4e]	8874	1			T3	9		T7	2		T25	2
valid_sources[0x4f]	8696	1			T8	1		T16	9		T17	4
valid_sources[0x50]	11017	1			T1	1		T25	20		T16	11
valid_sources[0x51]	10504	1			T2	23		T25	5		T17	3
valid_sources[0x52]	8989	1			T1	29		T2	22		T25	1
valid_sources[0x53]	8813	1			T6	7		T16	13		T17	1
valid_sources[0x54]	8666	1			T3	6		T25	13		T16	3
valid_sources[0x55]	9575	1			T16	4		T17	1		T24	72
valid_sources[0x56]	9261	1			T25	4		T16	9		T24	97
valid_sources[0x57]	9002	1			T2	18		T25	4		T16	4
valid_sources[0x58]	8720	1			T2	7		T16	2		T17	2
valid_sources[0x59]	8925	1			T3	1		T7	1		T25	1
valid_sources[0x5a]	8447	1			T1	31		T2	19		T9	6
valid_sources[0x5b]	8793	1			T2	18		T9	10		T16	1
valid_sources[0x5c]	14478	1			T9	2		T25	4		T16	5
valid_sources[0x5d]	8427	1			T7	2		T16	18		T17	4
valid_sources[0x5e]	9198	1			T8	1		T25	3		T16	13
valid_sources[0x5f]	8872	1			T9	2		T7	8		T16	11
valid_sources[0x60]	8930	1			T6	3		T16	1		T17	4
valid_sources[0x61]	9022	1			T2	5		T9	3		T16	8
valid_sources[0x62]	8734	1			T16	5		T17	1		T24	85
valid_sources[0x63]	9915	1			T9	1		T17	1		T24	78
valid_sources[0x64]	12703	1			T6	1		T7	6		T16	4
valid_sources[0x65]	9014	1			T9	1		T6	3		T16	1
valid_sources[0x66]	10232	1			T2	5		T8	1		T25	10
valid_sources[0x67]	12390	1			T3	5		T7	1		T16	2
valid_sources[0x68]	9059	1			T8	1		T16	8		T17	4
valid_sources[0x69]	8485	1			T8	1		T9	2		T16	2
valid_sources[0x6a]	9525	1			T16	14		T24	81		T80	7
valid_sources[0x6b]	9011	1			T16	2		T24	64		T80	3
valid_sources[0x6c]	85999	1			T2	4		T9	2		T7	42
valid_sources[0x6d]	87301	1			T1	1		T8	1		T9	9
valid_sources[0x6e]	11010	1			T16	1		T17	5		T24	79
valid_sources[0x6f]	10048	1			T9	2		T25	6		T17	5
valid_sources[0x70]	9690	1			T2	5		T7	1		T25	3
valid_sources[0x71]	11412	1			T9	3		T16	11		T17	1
valid_sources[0x72]	23042	1			T7	2		T25	25		T16	16
valid_sources[0x73]	8756	1			T25	3		T16	1		T17	3
valid_sources[0x74]	8904	1			T2	4		T6	7		T25	4
valid_sources[0x75]	8809	1			T3	8		T16	4		T17	1
valid_sources[0x76]	9697	1			T9	4		T25	3		T16	3
valid_sources[0x77]	11952	1			T2	22		T25	11		T16	1
valid_sources[0x78]	9093	1			T25	9		T16	2		T24	91
valid_sources[0x79]	9057	1			T9	3		T16	7		T17	2
valid_sources[0x7a]	8711	1			T2	5		T6	44		T25	4
valid_sources[0x7b]	8747	1			T2	19		T25	10		T16	22
valid_sources[0x7c]	15627	1			T2	4		T3	12		T7	1
valid_sources[0x7d]	8555	1			T8	1		T25	4		T16	5
valid_sources[0x7e]	8604	1			T2	2		T3	8		T25	1
valid_sources[0x7f]	8721	1			T25	5		T16	5		T17	3
valid_sources[0x80]	8687	1			T2	1		T3	3		T7	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1266657

1

T1

56

T2

256

T3

56

values[0x0]

all_enables

biggest_size

144607

1

T1

23

T2

172

T3

63

values[0x1]

all_enables

biggest_size

143658

1

T1

24

T2

197

T3

50