Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	103521912	12604	0	0
claim_transition_if_regwen_rd_A	103521912	782	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103521912	12604	0	0
T40	0	4	0	0
T78	193512	3	0	0
T79	0	2	0	0
T87	0	8	0	0
T102	0	12	0	0
T106	0	15	0	0
T138	0	17	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	2	0	0
T142	6738	0	0	0
T143	208681	0	0	0
T144	1174	0	0	0
T145	1024	0	0	0
T146	8626	0	0	0
T147	3969	0	0	0
T148	1170	0	0	0
T149	17290	0	0	0
T150	10395	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103521912	782	0	0
T40	0	8	0	0
T42	0	5	0	0
T78	193512	8	0	0
T79	0	3	0	0
T101	0	7	0	0
T139	0	4	0	0
T142	6738	0	0	0
T143	208681	0	0	0
T144	1174	0	0	0
T145	1024	0	0	0
T146	8626	0	0	0
T147	3969	0	0	0
T148	1170	0	0	0
T149	17290	0	0	0
T150	10395	0	0	0
T151	0	2	0	0
T152	0	4	0	0
T153	0	9	0	0
T154	0	9	0	0