Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1064002	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1270742

1

T1

7547

T2

1999

T3

210

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2015454	1			T1	13038		T2	3093		T3	159
values[0x0]	159207	1			T1	603		T2	256		T3	68
values[0x1]	160083	1			T1	569		T2	280		T3	84

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	843360	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1491384

1

T1

8977

T2

2326

T3

226

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8185	1			T3	2		T9	6		T10	16
valid_sources[0x01]	8123	1			T9	13		T10	6		T11	6
valid_sources[0x02]	6940	1			T3	2		T10	8		T11	2
valid_sources[0x03]	6870	1			T3	1		T9	1		T10	10
valid_sources[0x04]	13949	1			T9	2		T10	15		T11	12
valid_sources[0x05]	8215	1			T3	1		T9	3		T11	2
valid_sources[0x06]	7103	1			T9	5		T10	1		T11	5
valid_sources[0x07]	7434	1			T3	2		T9	2		T10	6
valid_sources[0x08]	8448	1			T9	6		T10	3		T11	2
valid_sources[0x09]	13862	1			T3	1		T9	5		T10	2
valid_sources[0x0a]	7239	1			T9	7		T10	7		T11	2
valid_sources[0x0b]	7767	1			T3	1		T9	7		T10	4
valid_sources[0x0c]	6566	1			T3	6		T9	2		T10	3
valid_sources[0x0d]	7356	1			T3	2		T9	9		T10	2
valid_sources[0x0e]	7031	1			T3	2		T9	2		T10	2
valid_sources[0x0f]	6810	1			T3	2		T9	4		T10	1
valid_sources[0x10]	7930	1			T3	1		T9	10		T10	6
valid_sources[0x11]	10477	1			T3	1		T9	6		T10	5
valid_sources[0x12]	6972	1			T9	1		T10	4		T11	8
valid_sources[0x13]	7192	1			T3	1		T9	17		T10	9
valid_sources[0x14]	7217	1			T3	2		T9	9		T10	2
valid_sources[0x15]	8455	1			T9	3		T10	4		T11	13
valid_sources[0x16]	7236	1			T3	2		T9	12		T11	10
valid_sources[0x17]	6623	1			T9	4		T10	6		T11	5
valid_sources[0x18]	12434	1			T9	10		T10	1		T11	7
valid_sources[0x19]	7045	1			T3	1		T9	2		T10	9
valid_sources[0x1a]	7262	1			T3	1		T9	1		T11	2
valid_sources[0x1b]	6790	1			T9	9		T10	4		T11	7
valid_sources[0x1c]	6725	1			T3	1		T9	6		T10	9
valid_sources[0x1d]	7043	1			T9	2		T10	8		T11	9
valid_sources[0x1e]	7059	1			T3	1		T9	8		T11	3
valid_sources[0x1f]	6975	1			T3	1		T10	1		T11	2
valid_sources[0x20]	7051	1			T3	3		T9	3		T10	8
valid_sources[0x21]	7036	1			T3	1		T9	1		T11	8
valid_sources[0x22]	6950	1			T3	1		T9	1		T10	1
valid_sources[0x23]	12990	1			T3	1		T9	1		T10	3
valid_sources[0x24]	19859	1			T3	2		T9	7		T10	2
valid_sources[0x25]	7069	1			T3	1		T9	3		T10	2
valid_sources[0x26]	6822	1			T9	7		T10	8		T5	482
valid_sources[0x27]	9079	1			T3	1		T9	15		T10	4
valid_sources[0x28]	8656	1			T3	1		T9	7		T10	3
valid_sources[0x29]	9494	1			T9	9		T10	4		T11	1
valid_sources[0x2a]	7252	1			T3	1		T9	5		T10	2
valid_sources[0x2b]	8844	1			T3	2		T9	5		T10	9
valid_sources[0x2c]	6583	1			T3	1		T10	3		T11	3
valid_sources[0x2d]	7118	1			T9	5		T10	3		T11	6
valid_sources[0x2e]	6971	1			T3	2		T9	4		T11	11
valid_sources[0x2f]	41712	1			T3	4		T9	1		T10	1
valid_sources[0x30]	8205	1			T9	2		T10	7		T11	12
valid_sources[0x31]	7470	1			T9	2		T10	6		T11	3
valid_sources[0x32]	6869	1			T3	1		T9	2		T10	2
valid_sources[0x33]	7059	1			T3	3		T9	4		T10	3
valid_sources[0x34]	8481	1			T3	3		T9	4		T10	12
valid_sources[0x35]	6812	1			T3	4		T9	13		T10	10
valid_sources[0x36]	8531	1			T9	6		T11	1		T5	468
valid_sources[0x37]	6862	1			T3	1		T9	12		T10	14
valid_sources[0x38]	11821	1			T3	1		T9	1		T10	6
valid_sources[0x39]	6999	1			T9	2		T10	12		T11	5
valid_sources[0x3a]	7066	1			T9	7		T10	4		T11	2
valid_sources[0x3b]	6858	1			T9	2		T10	5		T11	7
valid_sources[0x3c]	6532	1			T3	1		T9	3		T10	5
valid_sources[0x3d]	7668	1			T9	5		T10	2		T11	2
valid_sources[0x3e]	6634	1			T9	5		T11	4		T5	514
valid_sources[0x3f]	6822	1			T3	1		T9	4		T10	7
valid_sources[0x40]	7097	1			T9	2		T5	477		T20	7
valid_sources[0x41]	7150	1			T3	1		T9	13		T10	3
valid_sources[0x42]	7833	1			T9	8		T11	12		T5	507
valid_sources[0x43]	9990	1			T9	9		T11	2		T5	470
valid_sources[0x44]	6832	1			T9	9		T11	11		T5	492
valid_sources[0x45]	8218	1			T9	1		T10	5		T11	5
valid_sources[0x46]	6885	1			T3	4		T9	8		T10	2
valid_sources[0x47]	10284	1			T9	5		T11	6		T5	481
valid_sources[0x48]	7227	1			T3	1		T9	8		T11	10
valid_sources[0x49]	7157	1			T3	1		T9	5		T5	488
valid_sources[0x4a]	15969	1			T3	5		T9	5		T10	2
valid_sources[0x4b]	6779	1			T3	1		T9	3		T11	5
valid_sources[0x4c]	21644	1			T1	14210		T9	2		T10	1
valid_sources[0x4d]	8061	1			T3	1		T9	6		T11	7
valid_sources[0x4e]	6913	1			T3	1		T9	1		T10	1
valid_sources[0x4f]	8588	1			T9	2		T10	13		T11	21
valid_sources[0x50]	6503	1			T3	1		T9	1		T10	11
valid_sources[0x51]	6859	1			T3	2		T9	2		T11	1
valid_sources[0x52]	6971	1			T9	6		T11	2		T5	501
valid_sources[0x53]	6968	1			T9	6		T10	5		T11	6
valid_sources[0x54]	6912	1			T9	6		T11	13		T5	513
valid_sources[0x55]	7308	1			T9	4		T10	2		T5	511
valid_sources[0x56]	7103	1			T9	5		T10	4		T11	1
valid_sources[0x57]	7107	1			T3	2		T9	4		T10	4
valid_sources[0x58]	7003	1			T3	4		T9	16		T10	5
valid_sources[0x59]	7072	1			T3	1		T9	8		T10	2
valid_sources[0x5a]	7445	1			T3	3		T9	8		T10	7
valid_sources[0x5b]	6858	1			T9	6		T10	7		T11	1
valid_sources[0x5c]	7894	1			T3	1		T9	1		T10	12
valid_sources[0x5d]	6983	1			T3	4		T9	5		T10	7
valid_sources[0x5e]	17565	1			T3	5		T9	9		T10	5
valid_sources[0x5f]	7492	1			T9	3		T11	1		T5	502
valid_sources[0x60]	8329	1			T9	4		T10	6		T11	6
valid_sources[0x61]	7184	1			T9	2		T10	2		T11	7
valid_sources[0x62]	7734	1			T3	2		T9	4		T10	2
valid_sources[0x63]	19460	1			T3	3		T9	11		T10	1
valid_sources[0x64]	7396	1			T3	1		T9	8		T10	2
valid_sources[0x65]	7244	1			T9	2		T10	4		T11	18
valid_sources[0x66]	7194	1			T3	4		T9	3		T10	1
valid_sources[0x67]	7025	1			T3	1		T9	8		T11	18
valid_sources[0x68]	7092	1			T9	1		T11	6		T5	458
valid_sources[0x69]	6953	1			T3	1		T9	4		T10	6
valid_sources[0x6a]	7180	1			T3	1		T9	8		T11	9
valid_sources[0x6b]	9155	1			T3	2		T9	11		T10	2
valid_sources[0x6c]	7421	1			T3	2		T9	2		T10	4
valid_sources[0x6d]	43550	1			T3	2		T9	9		T10	2
valid_sources[0x6e]	10951	1			T3	1		T9	8		T10	8
valid_sources[0x6f]	7158	1			T3	3		T10	3		T11	4
valid_sources[0x70]	7621	1			T3	2		T9	4		T10	8
valid_sources[0x71]	6626	1			T9	11		T10	1		T11	11
valid_sources[0x72]	7207	1			T3	3		T9	4		T10	4
valid_sources[0x73]	6965	1			T9	7		T10	1		T11	12
valid_sources[0x74]	8338	1			T3	1		T9	5		T10	3
valid_sources[0x75]	7288	1			T3	3		T10	1		T11	7
valid_sources[0x76]	6954	1			T9	11		T10	6		T11	6
valid_sources[0x77]	6881	1			T3	1		T9	9		T10	1
valid_sources[0x78]	6662	1			T9	9		T10	13		T11	9
valid_sources[0x79]	7130	1			T9	1		T10	4		T11	11
valid_sources[0x7a]	7044	1			T3	1		T9	2		T11	3
valid_sources[0x7b]	7175	1			T3	5		T9	4		T10	12
valid_sources[0x7c]	7246	1			T9	5		T10	4		T11	12
valid_sources[0x7d]	7203	1			T9	4		T11	11		T5	509
valid_sources[0x7e]	9871	1			T9	3		T10	3		T11	6
valid_sources[0x7f]	6859	1			T3	1		T9	6		T10	4
valid_sources[0x80]	6893	1			T3	1		T9	2		T10	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

995894

1

T1

6533

T2

1537

T3

77

values[0x0]

all_enables

biggest_size

137963

1

T1

526

T2

223

T3

57

values[0x1]

all_enables

biggest_size

136885

1

T1

488

T2

239

T3

76