Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	83701278	14113	0	0
claim_transition_if_regwen_rd_A	83701278	1113	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83701278	14113	0	0
T43	0	6	0	0
T47	24835	0	0	0
T64	829862	7	0	0
T65	146813	0	0	0
T86	18686	0	0	0
T90	0	5	0	0
T92	0	2	0	0
T148	0	7	0	0
T149	0	1	0	0
T150	0	2	0	0
T151	0	3	0	0
T152	0	1	0	0
T153	0	3	0	0
T154	27343	0	0	0
T155	5404	0	0	0
T156	30960	0	0	0
T157	12229	0	0	0
T158	3789	0	0	0
T159	150064	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83701278	1113	0	0
T29	9908	0	0	0
T48	41811	0	0	0
T90	728740	3	0	0
T92	0	6	0	0
T113	602573	0	0	0
T115	0	2	0	0
T117	0	1	0	0
T118	0	61	0	0
T119	0	32	0	0
T121	0	8	0	0
T149	0	9	0	0
T160	0	9	0	0
T161	0	3	0	0
T162	1125	0	0	0
T163	44604	0	0	0
T164	38002	0	0	0
T165	67134	0	0	0
T166	4803	0	0	0
T167	26365	0	0	0