Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1193406	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1400203

1

T1

1002

T2

939

T3

13720

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2265368	1			T1	878		T2	799		T3	22777
values[0x0]	163724	1			T1	335		T2	338		T3	1468
values[0x1]	164517	1			T1	361		T2	302		T3	1500

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	945706	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1647903

1

T1

1140

T2

1045

T3

16217

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5874	1			T1	9		T2	5		T3	102
valid_sources[0x01]	6087	1			T1	5		T2	4		T3	133
valid_sources[0x02]	6111	1			T1	7		T2	12		T3	56
valid_sources[0x03]	8272	1			T1	10		T2	7		T3	94
valid_sources[0x04]	33096	1			T1	7		T2	6		T3	140
valid_sources[0x05]	5924	1			T1	7		T2	4		T3	93
valid_sources[0x06]	7514	1			T1	6		T2	2		T3	75
valid_sources[0x07]	5949	1			T1	10		T2	2		T3	166
valid_sources[0x08]	6157	1			T1	5		T2	3		T3	157
valid_sources[0x09]	7381	1			T1	2		T2	6		T3	130
valid_sources[0x0a]	6861	1			T1	4		T2	3		T3	140
valid_sources[0x0b]	5961	1			T1	7		T2	12		T3	129
valid_sources[0x0c]	5855	1			T1	4		T2	3		T3	138
valid_sources[0x0d]	6154	1			T1	8		T2	7		T3	90
valid_sources[0x0e]	6237	1			T1	9		T2	6		T3	266
valid_sources[0x0f]	6349	1			T1	4		T2	10		T3	133
valid_sources[0x10]	6200	1			T1	9		T2	16		T3	97
valid_sources[0x11]	5730	1			T1	1		T2	9		T3	133
valid_sources[0x12]	6114	1			T1	6		T2	3		T3	78
valid_sources[0x13]	6039	1			T1	3		T2	7		T3	44
valid_sources[0x14]	6204	1			T1	6		T2	17		T3	139
valid_sources[0x15]	5879	1			T1	10		T2	2		T3	112
valid_sources[0x16]	6306	1			T1	3		T2	5		T3	67
valid_sources[0x17]	5893	1			T1	5		T3	131		T8	32
valid_sources[0x18]	7749	1			T1	5		T2	5		T3	75
valid_sources[0x19]	7553	1			T1	7		T3	155		T7	1
valid_sources[0x1a]	5819	1			T1	9		T2	3		T3	33
valid_sources[0x1b]	6100	1			T1	9		T2	1		T3	114
valid_sources[0x1c]	7498	1			T1	4		T2	5		T3	185
valid_sources[0x1d]	6531	1			T1	3		T2	3		T3	88
valid_sources[0x1e]	6009	1			T1	9		T2	1		T3	67
valid_sources[0x1f]	5886	1			T1	6		T2	8		T3	102
valid_sources[0x20]	6954	1			T1	5		T2	8		T3	28
valid_sources[0x21]	6156	1			T1	8		T2	5		T3	81
valid_sources[0x22]	7484	1			T1	8		T2	10		T3	60
valid_sources[0x23]	9162	1			T1	7		T2	6		T3	109
valid_sources[0x24]	8242	1			T2	5		T3	135		T8	17
valid_sources[0x25]	5789	1			T1	6		T2	3		T3	92
valid_sources[0x26]	7737	1			T1	3		T2	6		T3	55
valid_sources[0x27]	6277	1			T1	8		T2	5		T3	96
valid_sources[0x28]	6133	1			T1	8		T2	7		T3	69
valid_sources[0x29]	6100	1			T1	8		T2	4		T3	128
valid_sources[0x2a]	20963	1			T1	5		T2	1		T3	244
valid_sources[0x2b]	6046	1			T1	8		T2	10		T3	84
valid_sources[0x2c]	6994	1			T1	8		T2	9		T3	126
valid_sources[0x2d]	5923	1			T1	6		T2	5		T3	122
valid_sources[0x2e]	5734	1			T1	5		T2	10		T3	67
valid_sources[0x2f]	6242	1			T1	11		T2	3		T3	117
valid_sources[0x30]	7399	1			T1	3		T2	8		T3	110
valid_sources[0x31]	43902	1			T1	6		T2	9		T3	100
valid_sources[0x32]	6106	1			T1	11		T2	6		T3	40
valid_sources[0x33]	6344	1			T1	5		T2	4		T3	94
valid_sources[0x34]	6184	1			T1	3		T2	5		T3	87
valid_sources[0x35]	22848	1			T1	7		T2	1		T3	63
valid_sources[0x36]	5987	1			T1	4		T2	5		T3	71
valid_sources[0x37]	5994	1			T1	7		T2	12		T3	80
valid_sources[0x38]	29867	1			T1	3		T2	6		T3	53
valid_sources[0x39]	5776	1			T1	3		T2	5		T3	60
valid_sources[0x3a]	6346	1			T1	9		T2	2		T3	114
valid_sources[0x3b]	6209	1			T1	7		T2	13		T3	79
valid_sources[0x3c]	5950	1			T1	11		T2	5		T3	51
valid_sources[0x3d]	39953	1			T1	7		T2	2		T3	40
valid_sources[0x3e]	5866	1			T1	5		T2	6		T3	118
valid_sources[0x3f]	7606	1			T1	7		T2	8		T3	35
valid_sources[0x40]	6028	1			T1	5		T2	6		T3	84
valid_sources[0x41]	7966	1			T1	10		T2	7		T3	138
valid_sources[0x42]	6841	1			T1	3		T2	7		T3	146
valid_sources[0x43]	6043	1			T1	10		T2	8		T3	121
valid_sources[0x44]	7159	1			T1	6		T2	1		T3	111
valid_sources[0x45]	7375	1			T1	12		T2	2		T3	123
valid_sources[0x46]	259511	1			T1	2		T3	83		T7	2
valid_sources[0x47]	6214	1			T1	9		T2	8		T3	108
valid_sources[0x48]	7014	1			T1	5		T2	4		T3	90
valid_sources[0x49]	10272	1			T1	2		T2	4		T3	128
valid_sources[0x4a]	8976	1			T1	4		T2	6		T3	186
valid_sources[0x4b]	6006	1			T1	3		T2	2		T3	120
valid_sources[0x4c]	6123	1			T1	3		T2	3		T3	79
valid_sources[0x4d]	6010	1			T1	4		T2	4		T3	156
valid_sources[0x4e]	7113	1			T1	6		T2	1		T3	100
valid_sources[0x4f]	5856	1			T1	7		T2	3		T3	79
valid_sources[0x50]	5897	1			T1	9		T2	6		T3	129
valid_sources[0x51]	52088	1			T1	9		T2	2		T3	156
valid_sources[0x52]	6858	1			T1	3		T2	9		T3	246
valid_sources[0x53]	5715	1			T1	10		T2	7		T3	91
valid_sources[0x54]	6050	1			T1	6		T2	7		T3	146
valid_sources[0x55]	7549	1			T1	7		T2	4		T3	44
valid_sources[0x56]	6349	1			T1	10		T2	7		T3	111
valid_sources[0x57]	5950	1			T1	10		T2	1		T3	91
valid_sources[0x58]	7011	1			T1	5		T2	11		T3	69
valid_sources[0x59]	7287	1			T1	6		T2	5		T3	45
valid_sources[0x5a]	5904	1			T1	3		T2	9		T3	87
valid_sources[0x5b]	5917	1			T1	6		T2	7		T3	75
valid_sources[0x5c]	7586	1			T1	7		T2	4		T3	117
valid_sources[0x5d]	7110	1			T1	4		T2	6		T3	132
valid_sources[0x5e]	5834	1			T1	5		T2	8		T3	59
valid_sources[0x5f]	6313	1			T1	8		T2	9		T3	84
valid_sources[0x60]	5806	1			T1	3		T2	4		T3	89
valid_sources[0x61]	46942	1			T1	9		T2	4		T3	126
valid_sources[0x62]	8948	1			T1	5		T2	5		T3	52
valid_sources[0x63]	6037	1			T1	7		T2	10		T3	64
valid_sources[0x64]	5746	1			T1	5		T2	9		T3	124
valid_sources[0x65]	6903	1			T1	8		T2	5		T3	183
valid_sources[0x66]	6656	1			T1	9		T2	7		T3	88
valid_sources[0x67]	6176	1			T1	8		T2	7		T3	57
valid_sources[0x68]	8179	1			T1	6		T2	14		T3	73
valid_sources[0x69]	5696	1			T1	7		T2	3		T3	26
valid_sources[0x6a]	6165	1			T1	7		T2	1		T3	108
valid_sources[0x6b]	30443	1			T1	3		T2	9		T3	123
valid_sources[0x6c]	7962	1			T1	4		T2	6		T3	15
valid_sources[0x6d]	81509	1			T1	7		T2	5		T3	44
valid_sources[0x6e]	7627	1			T1	3		T2	1		T3	120
valid_sources[0x6f]	5954	1			T1	2		T2	1		T3	73
valid_sources[0x70]	11301	1			T1	10		T2	4		T3	107
valid_sources[0x71]	17142	1			T1	14		T2	13		T3	107
valid_sources[0x72]	6096	1			T1	11		T2	8		T3	67
valid_sources[0x73]	5924	1			T1	10		T2	3		T3	57
valid_sources[0x74]	6085	1			T1	7		T2	9		T3	107
valid_sources[0x75]	5997	1			T1	8		T2	3		T3	80
valid_sources[0x76]	6745	1			T1	9		T2	1		T3	80
valid_sources[0x77]	5839	1			T1	7		T2	3		T3	79
valid_sources[0x78]	5926	1			T1	5		T3	142		T4	5
valid_sources[0x79]	6553	1			T1	5		T2	3		T3	33
valid_sources[0x7a]	6097	1			T1	3		T2	1		T3	111
valid_sources[0x7b]	7038	1			T1	4		T2	3		T3	75
valid_sources[0x7c]	5880	1			T1	3		T2	2		T3	54
valid_sources[0x7d]	5769	1			T1	4		T2	2		T3	50
valid_sources[0x7e]	6234	1			T1	7		T2	7		T3	123
valid_sources[0x7f]	6024	1			T1	7		T3	150		T8	7
valid_sources[0x80]	5738	1			T1	10		T2	1		T3	105

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1117777

1

T1

401

T2

390

T3

11163

values[0x0]

all_enables

biggest_size

141766

1

T1

288

T2

286

T3

1260

values[0x1]

all_enables

biggest_size

140660

1

T1

313

T2

263

T3

1297