Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	97788350	13504	0	0
claim_transition_if_regwen_rd_A	97788350	1312	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97788350	13504	0	0
T16	259765	1	0	0
T17	32356	0	0	0
T20	435853	0	0	0
T30	0	8	0	0
T31	0	4	0	0
T33	40934	0	0	0
T34	0	10	0	0
T67	7016	0	0	0
T78	30065	0	0	0
T100	0	1	0	0
T137	0	9	0	0
T138	0	5	0	0
T139	0	1	0	0
T140	0	3	0	0
T141	0	7	0	0
T142	26889	0	0	0
T143	976	0	0	0
T144	41424	0	0	0
T145	4500	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97788350	1312	0	0
T3	204965	2	0	0
T4	49310	0	0	0
T5	10731	0	0	0
T6	20339	0	0	0
T7	1559	0	0	0
T8	83017	0	0	0
T9	6687	0	0	0
T10	6612	0	0	0
T11	61833	0	0	0
T12	34988	0	0	0
T16	0	3	0	0
T31	0	14	0	0
T70	0	15	0	0
T83	0	4	0	0
T100	0	19	0	0
T106	0	9	0	0
T113	0	43	0	0
T139	0	17	0	0
T146	0	8	0	0