Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57817 |
1 |
|
|
T1 |
12 |
|
T2 |
14 |
|
T4 |
16 |
auto[1] |
2059 |
1 |
|
|
T14 |
8 |
|
T15 |
28 |
|
T16 |
7 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59119 |
1 |
|
|
T1 |
12 |
|
T2 |
14 |
|
T4 |
16 |
auto[1] |
757 |
1 |
|
|
T20 |
10 |
|
T23 |
11 |
|
T54 |
15 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57647 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T4 |
16 |
auto[1] |
2229 |
1 |
|
|
T2 |
1 |
|
T9 |
9 |
|
T15 |
49 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57651 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T4 |
16 |
auto[1] |
2225 |
1 |
|
|
T2 |
1 |
|
T9 |
7 |
|
T15 |
36 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57680 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T4 |
16 |
auto[1] |
2196 |
1 |
|
|
T2 |
1 |
|
T9 |
5 |
|
T15 |
38 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
54432 |
1 |
|
|
T1 |
5 |
|
T2 |
6 |
|
T9 |
79 |
no_err_inj |
5444 |
1 |
|
|
T1 |
7 |
|
T2 |
8 |
|
T4 |
16 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57745 |
1 |
|
|
T1 |
12 |
|
T2 |
14 |
|
T4 |
16 |
auto[1] |
2131 |
1 |
|
|
T14 |
12 |
|
T15 |
31 |
|
T16 |
13 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59132 |
1 |
|
|
T1 |
12 |
|
T2 |
14 |
|
T4 |
16 |
auto[1] |
744 |
1 |
|
|
T20 |
7 |
|
T23 |
17 |
|
T54 |
18 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
41061 |
1 |
|
|
T1 |
12 |
|
T9 |
79 |
|
T11 |
20 |
auto[1] |
18815 |
1 |
|
|
T2 |
14 |
|
T4 |
16 |
|
T14 |
87 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57595 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T4 |
16 |
auto[1] |
2281 |
1 |
|
|
T2 |
1 |
|
T9 |
5 |
|
T15 |
34 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57621 |
1 |
|
|
T1 |
10 |
|
T2 |
14 |
|
T4 |
16 |
auto[1] |
2255 |
1 |
|
|
T1 |
2 |
|
T9 |
10 |
|
T15 |
32 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57690 |
1 |
|
|
T1 |
11 |
|
T2 |
13 |
|
T4 |
16 |
auto[1] |
2186 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T9 |
11 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57772 |
1 |
|
|
T1 |
12 |
|
T2 |
14 |
|
T4 |
16 |
auto[1] |
2104 |
1 |
|
|
T14 |
10 |
|
T15 |
22 |
|
T16 |
13 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57067 |
1 |
|
|
T1 |
12 |
|
T2 |
14 |
|
T4 |
16 |
auto[1] |
2809 |
1 |
|
|
T24 |
3 |
|
T15 |
28 |
|
T52 |
1 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59191 |
1 |
|
|
T1 |
12 |
|
T2 |
14 |
|
T4 |
16 |
auto[1] |
685 |
1 |
|
|
T20 |
12 |
|
T23 |
10 |
|
T54 |
10 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59094 |
1 |
|
|
T1 |
12 |
|
T2 |
14 |
|
T4 |
16 |
auto[1] |
782 |
1 |
|
|
T20 |
12 |
|
T23 |
23 |
|
T54 |
22 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59137 |
1 |
|
|
T1 |
12 |
|
T2 |
14 |
|
T4 |
16 |
auto[1] |
739 |
1 |
|
|
T20 |
14 |
|
T23 |
8 |
|
T54 |
16 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56695 |
1 |
|
|
T4 |
16 |
|
T9 |
79 |
|
T11 |
20 |
auto[1] |
3181 |
1 |
|
|
T1 |
12 |
|
T2 |
14 |
|
T15 |
14 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56026 |
1 |
|
|
T1 |
12 |
|
T2 |
14 |
|
T4 |
16 |
auto[1] |
3850 |
1 |
|
|
T12 |
64 |
|
T39 |
82 |
|
T41 |
95 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57676 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T4 |
16 |
auto[1] |
2200 |
1 |
|
|
T2 |
1 |
|
T9 |
9 |
|
T15 |
49 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57544 |
1 |
|
|
T1 |
10 |
|
T2 |
14 |
|
T4 |
16 |
auto[1] |
2332 |
1 |
|
|
T1 |
2 |
|
T9 |
11 |
|
T15 |
35 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57669 |
1 |
|
|
T1 |
12 |
|
T2 |
14 |
|
T4 |
16 |
auto[1] |
2207 |
1 |
|
|
T9 |
12 |
|
T15 |
50 |
|
T57 |
1 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57767 |
1 |
|
|
T1 |
12 |
|
T2 |
14 |
|
T4 |
16 |
auto[1] |
2109 |
1 |
|
|
T14 |
15 |
|
T15 |
30 |
|
T16 |
17 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54003 |
1 |
|
|
T1 |
12 |
|
T2 |
14 |
|
T4 |
16 |
auto[1] |
5873 |
1 |
|
|
T13 |
92 |
|
T14 |
11 |
|
T15 |
20 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56329 |
1 |
|
|
T1 |
12 |
|
T2 |
14 |
|
T4 |
16 |
auto[1] |
3547 |
1 |
|
|
T21 |
53 |
|
T38 |
74 |
|
T53 |
51 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59876 |
1 |
|
|
T1 |
12 |
|
T2 |
14 |
|
T4 |
16 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57870 |
1 |
|
|
T1 |
12 |
|
T2 |
14 |
|
T4 |
16 |
auto[1] |
2006 |
1 |
|
|
T14 |
14 |
|
T15 |
25 |
|
T16 |
9 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57786 |
1 |
|
|
T1 |
12 |
|
T2 |
14 |
|
T4 |
16 |
auto[1] |
2090 |
1 |
|
|
T14 |
6 |
|
T15 |
27 |
|
T16 |
19 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57840 |
1 |
|
|
T1 |
12 |
|
T2 |
14 |
|
T4 |
16 |
auto[1] |
2036 |
1 |
|
|
T14 |
11 |
|
T15 |
30 |
|
T16 |
6 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
52793 |
1 |
|
|
T9 |
79 |
|
T12 |
64 |
|
T13 |
92 |
auto[0] |
no_err_inj |
3902 |
1 |
|
|
T4 |
16 |
|
T11 |
20 |
|
T15 |
104 |
auto[1] |
err_inj |
1639 |
1 |
|
|
T1 |
5 |
|
T2 |
6 |
|
T15 |
7 |
auto[1] |
no_err_inj |
1542 |
1 |
|
|
T1 |
7 |
|
T2 |
8 |
|
T15 |
7 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
54558 |
1 |
|
|
T4 |
16 |
|
T9 |
68 |
|
T11 |
20 |
auto[0] |
auto[1] |
2137 |
1 |
|
|
T9 |
11 |
|
T15 |
33 |
|
T77 |
12 |
auto[1] |
auto[0] |
2986 |
1 |
|
|
T1 |
10 |
|
T2 |
14 |
|
T15 |
12 |
auto[1] |
auto[1] |
195 |
1 |
|
|
T1 |
2 |
|
T15 |
2 |
|
T66 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
54636 |
1 |
|
|
T4 |
16 |
|
T9 |
69 |
|
T11 |
20 |
auto[0] |
auto[1] |
2059 |
1 |
|
|
T9 |
10 |
|
T15 |
31 |
|
T77 |
7 |
auto[1] |
auto[0] |
2985 |
1 |
|
|
T1 |
10 |
|
T2 |
14 |
|
T15 |
13 |
auto[1] |
auto[1] |
196 |
1 |
|
|
T1 |
2 |
|
T15 |
1 |
|
T57 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
54669 |
1 |
|
|
T4 |
16 |
|
T9 |
67 |
|
T11 |
20 |
auto[0] |
auto[1] |
2026 |
1 |
|
|
T9 |
12 |
|
T15 |
50 |
|
T77 |
7 |
auto[1] |
auto[0] |
3000 |
1 |
|
|
T1 |
12 |
|
T2 |
14 |
|
T15 |
14 |
auto[1] |
auto[1] |
181 |
1 |
|
|
T57 |
1 |
|
T198 |
1 |
|
T17 |
6 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
54637 |
1 |
|
|
T4 |
16 |
|
T9 |
72 |
|
T11 |
20 |
auto[0] |
auto[1] |
2058 |
1 |
|
|
T9 |
7 |
|
T15 |
36 |
|
T77 |
9 |
auto[1] |
auto[0] |
3014 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T15 |
14 |
auto[1] |
auto[1] |
167 |
1 |
|
|
T2 |
1 |
|
T57 |
1 |
|
T66 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
54670 |
1 |
|
|
T4 |
16 |
|
T9 |
74 |
|
T11 |
20 |
auto[0] |
auto[1] |
2025 |
1 |
|
|
T9 |
5 |
|
T15 |
37 |
|
T77 |
7 |
auto[1] |
auto[0] |
3010 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T15 |
13 |
auto[1] |
auto[1] |
171 |
1 |
|
|
T2 |
1 |
|
T15 |
1 |
|
T57 |
2 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
54650 |
1 |
|
|
T4 |
16 |
|
T9 |
70 |
|
T11 |
20 |
auto[0] |
auto[1] |
2045 |
1 |
|
|
T9 |
9 |
|
T15 |
49 |
|
T77 |
7 |
auto[1] |
auto[0] |
2997 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T15 |
14 |
auto[1] |
auto[1] |
184 |
1 |
|
|
T2 |
1 |
|
T57 |
1 |
|
T66 |
2 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39810 |
1 |
|
|
T1 |
12 |
|
T9 |
79 |
|
T11 |
20 |
auto[0] |
auto[1] |
1251 |
1 |
|
|
T15 |
18 |
|
T16 |
7 |
|
T26 |
30 |
auto[1] |
auto[0] |
18007 |
1 |
|
|
T2 |
14 |
|
T4 |
16 |
|
T14 |
79 |
auto[1] |
auto[1] |
808 |
1 |
|
|
T14 |
8 |
|
T15 |
10 |
|
T26 |
6 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39786 |
1 |
|
|
T1 |
12 |
|
T9 |
79 |
|
T11 |
20 |
auto[0] |
auto[1] |
1275 |
1 |
|
|
T15 |
14 |
|
T16 |
13 |
|
T26 |
31 |
auto[1] |
auto[0] |
17959 |
1 |
|
|
T2 |
14 |
|
T4 |
16 |
|
T14 |
75 |
auto[1] |
auto[1] |
856 |
1 |
|
|
T14 |
12 |
|
T15 |
17 |
|
T26 |
6 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39427 |
1 |
|
|
T1 |
12 |
|
T9 |
79 |
|
T11 |
20 |
auto[0] |
auto[1] |
1634 |
1 |
|
|
T15 |
13 |
|
T52 |
1 |
|
T26 |
17 |
auto[1] |
auto[0] |
17640 |
1 |
|
|
T2 |
14 |
|
T4 |
16 |
|
T14 |
87 |
auto[1] |
auto[1] |
1175 |
1 |
|
|
T24 |
3 |
|
T15 |
15 |
|
T17 |
35 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39853 |
1 |
|
|
T1 |
12 |
|
T9 |
79 |
|
T11 |
20 |
auto[0] |
auto[1] |
1208 |
1 |
|
|
T15 |
8 |
|
T16 |
13 |
|
T26 |
23 |
auto[1] |
auto[0] |
17919 |
1 |
|
|
T2 |
14 |
|
T4 |
16 |
|
T14 |
77 |
auto[1] |
auto[1] |
896 |
1 |
|
|
T14 |
10 |
|
T15 |
14 |
|
T26 |
11 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36041 |
1 |
|
|
T1 |
12 |
|
T9 |
79 |
|
T11 |
20 |
auto[0] |
auto[1] |
5020 |
1 |
|
|
T13 |
92 |
|
T15 |
8 |
|
T16 |
7 |
auto[1] |
auto[0] |
17962 |
1 |
|
|
T2 |
14 |
|
T4 |
16 |
|
T14 |
76 |
auto[1] |
auto[1] |
853 |
1 |
|
|
T14 |
11 |
|
T15 |
12 |
|
T26 |
10 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39736 |
1 |
|
|
T1 |
10 |
|
T9 |
68 |
|
T11 |
20 |
auto[0] |
auto[1] |
1325 |
1 |
|
|
T1 |
2 |
|
T9 |
11 |
|
T15 |
15 |
auto[1] |
auto[0] |
17808 |
1 |
|
|
T2 |
14 |
|
T4 |
16 |
|
T14 |
87 |
auto[1] |
auto[1] |
1007 |
1 |
|
|
T15 |
20 |
|
T26 |
1 |
|
T17 |
27 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39773 |
1 |
|
|
T1 |
12 |
|
T9 |
70 |
|
T11 |
20 |
auto[0] |
auto[1] |
1288 |
1 |
|
|
T9 |
9 |
|
T15 |
24 |
|
T77 |
5 |
auto[1] |
auto[0] |
17903 |
1 |
|
|
T2 |
13 |
|
T4 |
16 |
|
T14 |
87 |
auto[1] |
auto[1] |
912 |
1 |
|
|
T2 |
1 |
|
T15 |
25 |
|
T26 |
1 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39745 |
1 |
|
|
T1 |
10 |
|
T9 |
69 |
|
T11 |
20 |
auto[0] |
auto[1] |
1316 |
1 |
|
|
T1 |
2 |
|
T9 |
10 |
|
T15 |
15 |
auto[1] |
auto[0] |
17876 |
1 |
|
|
T2 |
14 |
|
T4 |
16 |
|
T14 |
87 |
auto[1] |
auto[1] |
939 |
1 |
|
|
T15 |
17 |
|
T26 |
1 |
|
T17 |
23 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39715 |
1 |
|
|
T1 |
12 |
|
T9 |
74 |
|
T11 |
20 |
auto[0] |
auto[1] |
1346 |
1 |
|
|
T9 |
5 |
|
T15 |
19 |
|
T57 |
1 |
auto[1] |
auto[0] |
17880 |
1 |
|
|
T2 |
13 |
|
T4 |
16 |
|
T14 |
87 |
auto[1] |
auto[1] |
935 |
1 |
|
|
T2 |
1 |
|
T15 |
15 |
|
T26 |
1 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39742 |
1 |
|
|
T1 |
12 |
|
T9 |
72 |
|
T11 |
20 |
auto[0] |
auto[1] |
1319 |
1 |
|
|
T9 |
7 |
|
T15 |
21 |
|
T57 |
1 |
auto[1] |
auto[0] |
17909 |
1 |
|
|
T2 |
13 |
|
T4 |
16 |
|
T14 |
87 |
auto[1] |
auto[1] |
906 |
1 |
|
|
T2 |
1 |
|
T15 |
15 |
|
T17 |
36 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39747 |
1 |
|
|
T1 |
12 |
|
T9 |
70 |
|
T11 |
20 |
auto[0] |
auto[1] |
1314 |
1 |
|
|
T9 |
9 |
|
T15 |
25 |
|
T57 |
1 |
auto[1] |
auto[0] |
17900 |
1 |
|
|
T2 |
13 |
|
T4 |
16 |
|
T14 |
87 |
auto[1] |
auto[1] |
915 |
1 |
|
|
T2 |
1 |
|
T15 |
24 |
|
T26 |
1 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39883 |
1 |
|
|
T1 |
12 |
|
T9 |
79 |
|
T11 |
20 |
auto[0] |
auto[1] |
1178 |
1 |
|
|
T15 |
18 |
|
T16 |
6 |
|
T26 |
23 |
auto[1] |
auto[0] |
17957 |
1 |
|
|
T2 |
14 |
|
T4 |
16 |
|
T14 |
76 |
auto[1] |
auto[1] |
858 |
1 |
|
|
T14 |
11 |
|
T15 |
12 |
|
T26 |
9 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39812 |
1 |
|
|
T1 |
12 |
|
T9 |
79 |
|
T11 |
20 |
auto[0] |
auto[1] |
1249 |
1 |
|
|
T15 |
15 |
|
T16 |
19 |
|
T26 |
16 |
auto[1] |
auto[0] |
17974 |
1 |
|
|
T2 |
14 |
|
T4 |
16 |
|
T14 |
81 |
auto[1] |
auto[1] |
841 |
1 |
|
|
T14 |
6 |
|
T15 |
12 |
|
T26 |
6 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39432 |
1 |
|
|
T9 |
79 |
|
T11 |
20 |
|
T12 |
64 |
auto[0] |
auto[1] |
1629 |
1 |
|
|
T1 |
12 |
|
T57 |
14 |
|
T66 |
11 |
auto[1] |
auto[0] |
17263 |
1 |
|
|
T4 |
16 |
|
T14 |
87 |
|
T24 |
3 |
auto[1] |
auto[1] |
1552 |
1 |
|
|
T2 |
14 |
|
T15 |
14 |
|
T26 |
15 |