Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

124571006

1

T1

9598

T2

57340

T3

13478

auto[1]

1573509

1

T1

99

T2

197

T9

2871

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

124586409

1

T1

9400

T2

57243

T3

13478

auto[1]

1558106

1

T1

297

T2

294

T9

2673

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	8166590	1			T1	1183		T2	3362		T3	76
auto[IdleSt]	24378469	1			T1	984		T2	15326		T3	13402
auto[ClkMuxSt]	38627	1			T1	7		T2	8		T4	16
auto[CntIncrSt]	38356	1			T1	7		T2	8		T4	16
auto[CntProgSt]	1902105	1			T1	198		T2	304		T4	48
auto[TransCheckSt]	29464	1			T1	7		T2	8		T4	16
auto[TokenHashSt]	54426756	1			T1	4935		T2	581		T4	806
auto[FlashRmaSt]	31032	1			T1	7		T2	16		T4	16
auto[TokenCheck0St]	13869	1			T1	7		T2	8		T4	16
auto[TokenCheck1St]	10326	1			T1	7		T2	8		T4	16
auto[TransProgSt]	527076	1			T1	153		T2	381		T4	45
auto[PostTransSt]	14667521	1			T1	1244		T2	19936		T4	3935
auto[ScrapSt]	229752	1			T11	181		T12	6		T15	247
auto[EscalateSt]	7947237	1			T1	639		T2	9068		T9	7730
auto[InvalidSt]	13734999	1			T1	317		T2	8523		T9	7732

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2336	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	13734999	1			T1	317		T2	8523		T9	7732
EscalateSt	7947237	1			T1	639		T2	9068		T9	7730
ScrapSt	229752	1			T11	181		T12	6		T15	247
PostTransSt	14667521	1			T1	1244		T2	19936		T4	3935
TransProgSt	527076	1			T1	153		T2	381		T4	45
TokenCheck1St	10326	1			T1	7		T2	8		T4	16
TokenCheck0St	13869	1			T1	7		T2	8		T4	16
FlashRmaSt	31032	1			T1	7		T2	16		T4	16
TokenHashSt	54426756	1			T1	4935		T2	581		T4	806
TransCheckSt	29464	1			T1	7		T2	8		T4	16
CntProgSt	1902105	1			T1	198		T2	304		T4	48
CntIncrSt	38356	1			T1	7		T2	8		T4	16
ClkMuxSt	38627	1			T1	7		T2	8		T4	16
IdleSt	24378469	1			T1	984		T2	15326		T3	13402
ResetSt	8166590	1			T1	1183		T2	3362		T3	76
arcs[ResetSt=>IdleSt]	60063	1			T1	12		T2	14		T3	1
arcs[IdleSt=>ScrapSt]	293	1			T11	1		T12	2		T15	1
arcs[IdleSt=>ClkMuxSt]	38418	1			T1	7		T2	8		T4	16
arcs[ClkMuxSt=>CntIncrSt]	38356	1			T1	7		T2	8		T4	16
arcs[CntIncrSt=>PostTransSt]	2091	1			T14	6		T15	27		T16	19
arcs[CntIncrSt=>CntProgSt]	36189	1			T1	7		T2	8		T4	16
arcs[CntProgSt=>PostTransSt]	5564	1			T20	10		T14	6		T24	3
arcs[CntProgSt=>TransCheckSt]	29464	1			T1	7		T2	8		T4	16
arcs[TransCheckSt=>PostTransSt]	3785	1			T21	22		T14	11		T15	30
arcs[TransCheckSt=>TokenHashSt]	25576	1			T1	7		T2	8		T4	16
arcs[TokenHashSt=>PostTransSt]	10938	1			T13	92		T20	8		T21	10
arcs[TokenHashSt=>FlashRmaSt]	13962	1			T1	7		T2	8		T4	16
arcs[FlashRmaSt=>TokenCheck0St]	13869	1			T1	7		T2	8		T4	16
arcs[TokenCheck0St=>PostTransSt]	3516	1			T20	6		T21	9		T14	10
arcs[TokenCheck0St=>TokenCheck1St]	10326	1			T1	7		T2	8		T4	16
arcs[TokenCheck1St=>PostTransSt]	676	1			T21	12		T14	1		T15	2
arcs[TransProgSt=>PostTransSt]	8696	1			T1	7		T2	8		T4	16
arcs[IdleSt=>EscalateSt]	190	1			T39	5		T41	9		T42	10
arcs[ClkMuxSt=>EscalateSt]	62	1			T12	2		T39	3		T40	2
arcs[CntIncrSt=>EscalateSt]	76	1			T39	2		T41	2		T40	1
arcs[CntProgSt=>EscalateSt]	1161	1			T12	29		T39	9		T41	23
arcs[TransCheckSt=>EscalateSt]	103	1			T39	11		T41	4		T40	1
arcs[TokenHashSt=>EscalateSt]	675	1			T12	5		T15	3		T39	21
arcs[FlashRmaSt=>EscalateSt]	93	1			T12	1		T15	1		T39	2
arcs[TokenCheck0St=>EscalateSt]	27	1			T41	1		T46	1		T47	1
arcs[TokenCheck1St=>EscalateSt]	147	1			T12	2		T39	3		T41	3
arcs[TransProgSt=>EscalateSt]	807	1			T12	18		T39	9		T41	22
arcs[PostTransSt=>EscalateSt]	5823	1			T12	2		T20	10		T14	8
arcs[InvalidSt=>EscalateSt]	16519	1			T1	4		T2	5		T9	56

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8166412	1			T1	1183		T2	3362		T3	76
auto[0]	auto[IdleSt]	24378338	1			T1	984		T2	15326		T3	13402
auto[0]	auto[ClkMuxSt]	38589	1			T1	7		T2	8		T4	16
auto[0]	auto[CntIncrSt]	38301	1			T1	7		T2	8		T4	16
auto[0]	auto[CntProgSt]	1901324	1			T1	198		T2	304		T4	48
auto[0]	auto[TransCheckSt]	29394	1			T1	7		T2	8		T4	16
auto[0]	auto[TokenHashSt]	54426312	1			T1	4935		T2	581		T4	806
auto[0]	auto[FlashRmaSt]	30961	1			T1	7		T2	16		T4	16
auto[0]	auto[TokenCheck0St]	13853	1			T1	7		T2	8		T4	16
auto[0]	auto[TokenCheck1St]	10227	1			T1	7		T2	8		T4	16
auto[0]	auto[TransProgSt]	526535	1			T1	153		T2	381		T4	45
auto[0]	auto[PostTransSt]	14664580	1			T1	1244		T2	19936		T4	3935
auto[0]	auto[ScrapSt]	229712	1			T11	181		T12	5		T15	247
auto[0]	auto[EscalateSt]	6387394	1			T1	541		T2	8873		T9	4888
auto[0]	auto[InvalidSt]	13726738	1			T1	316		T2	8521		T9	7703
auto[1]	auto[ResetSt]	178	1			T12	2		T41	7		T43	4
auto[1]	auto[IdleSt]	131	1			T39	5		T41	6		T42	9
auto[1]	auto[ClkMuxSt]	38	1			T40	1		T195	1		T46	1
auto[1]	auto[CntIncrSt]	55	1			T39	2		T40	1		T195	1
auto[1]	auto[CntProgSt]	781	1			T12	20		T39	5		T41	17
auto[1]	auto[TransCheckSt]	70	1			T39	9		T41	3		T195	2
auto[1]	auto[TokenHashSt]	444	1			T12	4		T15	1		T39	15
auto[1]	auto[FlashRmaSt]	71	1			T12	1		T15	1		T39	2
auto[1]	auto[TokenCheck0St]	16	1			T46	1		T196	1		T197	1
auto[1]	auto[TokenCheck1St]	99	1			T12	1		T39	2		T41	2
auto[1]	auto[TransProgSt]	541	1			T12	10		T39	6		T41	15
auto[1]	auto[PostTransSt]	2941	1			T12	1		T20	3		T14	4
auto[1]	auto[ScrapSt]	40	1			T12	1		T41	2		T43	1
auto[1]	auto[EscalateSt]	1559843	1			T1	98		T2	195		T9	2842
auto[1]	auto[InvalidSt]	8261	1			T1	1		T2	2		T9	29

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8166420	1			T1	1183		T2	3362		T3	76
auto[0]	auto[IdleSt]	24378347	1			T1	984		T2	15326		T3	13402
auto[0]	auto[ClkMuxSt]	38589	1			T1	7		T2	8		T4	16
auto[0]	auto[CntIncrSt]	38309	1			T1	7		T2	8		T4	16
auto[0]	auto[CntProgSt]	1901338	1			T1	198		T2	304		T4	48
auto[0]	auto[TransCheckSt]	29399	1			T1	7		T2	8		T4	16
auto[0]	auto[TokenHashSt]	54426334	1			T1	4935		T2	581		T4	806
auto[0]	auto[FlashRmaSt]	30977	1			T1	7		T2	16		T4	16
auto[0]	auto[TokenCheck0St]	13846	1			T1	7		T2	8		T4	16
auto[0]	auto[TokenCheck1St]	10229	1			T1	7		T2	8		T4	16
auto[0]	auto[TransProgSt]	526535	1			T1	153		T2	381		T4	45
auto[0]	auto[PostTransSt]	14664566	1			T1	1244		T2	19936		T4	3935
auto[0]	auto[ScrapSt]	229715	1			T11	181		T12	5		T15	247
auto[0]	auto[EscalateSt]	6402728	1			T1	345		T2	8777		T9	5084
auto[0]	auto[InvalidSt]	13726741	1			T1	314		T2	8520		T9	7705
auto[1]	auto[ResetSt]	170	1			T12	1		T41	1		T43	5
auto[1]	auto[IdleSt]	122	1			T39	3		T41	5		T42	5
auto[1]	auto[ClkMuxSt]	38	1			T12	2		T39	3		T40	1
auto[1]	auto[CntIncrSt]	47	1			T41	2		T195	1		T46	3
auto[1]	auto[CntProgSt]	767	1			T12	18		T39	7		T41	15
auto[1]	auto[TransCheckSt]	65	1			T39	5		T41	3		T40	1
auto[1]	auto[TokenHashSt]	422	1			T12	3		T15	2		T39	11
auto[1]	auto[FlashRmaSt]	55	1			T12	1		T39	1		T41	1
auto[1]	auto[TokenCheck0St]	23	1			T41	1		T47	1		T196	1
auto[1]	auto[TokenCheck1St]	97	1			T12	1		T39	3		T41	1
auto[1]	auto[TransProgSt]	541	1			T12	14		T39	7		T41	15
auto[1]	auto[PostTransSt]	2955	1			T12	2		T20	7		T14	4
auto[1]	auto[ScrapSt]	37	1			T12	1		T39	2		T41	2
auto[1]	auto[EscalateSt]	1544509	1			T1	294		T2	291		T9	2646
auto[1]	auto[InvalidSt]	8258	1			T1	3		T2	3		T9	27