Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1380454	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1587855

1

T2

928

T3

1

T10

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2643238	1			T2	719		T3	2		T4	590
values[0x0]	162251	1			T2	336		T10	28		T11	17
values[0x1]	162820	1			T2	336		T3	1		T10	31

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1094594	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1873715

1

T2

1018

T3

2

T10

23

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8461	1			T2	2		T10	1		T12	2
valid_sources[0x01]	32771	1			T13	15		T18	1		T21	4
valid_sources[0x02]	8428	1			T2	8		T13	6		T18	6
valid_sources[0x03]	9846	1			T2	4		T13	18		T18	3
valid_sources[0x04]	8669	1			T18	7		T21	2		T22	3
valid_sources[0x05]	8860	1			T10	2		T13	18		T18	3
valid_sources[0x06]	8822	1			T12	1		T18	5		T20	1
valid_sources[0x07]	8360	1			T2	6		T13	11		T18	6
valid_sources[0x08]	8972	1			T13	9		T18	5		T21	4
valid_sources[0x09]	8907	1			T13	6		T18	4		T21	10
valid_sources[0x0a]	25247	1			T2	24		T10	1		T12	1
valid_sources[0x0b]	13766	1			T13	8		T18	3		T26	9
valid_sources[0x0c]	8832	1			T2	4		T13	8		T18	2
valid_sources[0x0d]	9298	1			T12	1		T13	10		T18	6
valid_sources[0x0e]	8775	1			T2	2		T13	7		T26	41
valid_sources[0x0f]	8952	1			T18	4		T21	6		T22	3
valid_sources[0x10]	8779	1			T13	1		T18	4		T26	38
valid_sources[0x11]	8830	1			T2	36		T12	1		T13	16
valid_sources[0x12]	8853	1			T2	4		T10	1		T13	5
valid_sources[0x13]	9175	1			T2	12		T13	6		T18	1
valid_sources[0x14]	8996	1			T2	6		T12	1		T13	9
valid_sources[0x15]	8658	1			T13	11		T18	2		T26	11
valid_sources[0x16]	8577	1			T13	24		T18	7		T21	12
valid_sources[0x17]	8346	1			T2	15		T13	1		T18	7
valid_sources[0x18]	8104	1			T2	1		T12	2		T13	2
valid_sources[0x19]	8691	1			T13	9		T21	4		T22	5
valid_sources[0x1a]	9175	1			T2	3		T18	3		T20	1
valid_sources[0x1b]	9031	1			T2	5		T12	1		T13	21
valid_sources[0x1c]	8525	1			T2	5		T13	10		T18	1
valid_sources[0x1d]	10366	1			T10	2		T11	1		T13	14
valid_sources[0x1e]	8579	1			T2	10		T13	19		T18	4
valid_sources[0x1f]	8553	1			T2	7		T12	1		T13	9
valid_sources[0x20]	8573	1			T11	1		T13	8		T18	8
valid_sources[0x21]	9301	1			T10	1		T12	1		T13	10
valid_sources[0x22]	11891	1			T2	5		T12	1		T13	5
valid_sources[0x23]	8621	1			T2	8		T10	1		T12	2
valid_sources[0x24]	12365	1			T13	8		T18	4		T21	1
valid_sources[0x25]	8724	1			T11	2		T13	9		T18	5
valid_sources[0x26]	8823	1			T2	7		T10	1		T11	1
valid_sources[0x27]	8500	1			T13	4		T18	1		T21	12
valid_sources[0x28]	8738	1			T2	25		T12	2		T13	11
valid_sources[0x29]	10174	1			T10	1		T12	1		T13	24
valid_sources[0x2a]	8874	1			T2	3		T11	1		T12	3
valid_sources[0x2b]	12556	1			T2	11		T13	6		T18	6
valid_sources[0x2c]	9005	1			T2	1		T11	1		T13	3
valid_sources[0x2d]	11582	1			T2	2		T13	4		T18	2
valid_sources[0x2e]	8558	1			T2	24		T10	1		T13	8
valid_sources[0x2f]	8448	1			T13	2		T18	3		T21	10
valid_sources[0x30]	8577	1			T12	1		T13	5		T18	4
valid_sources[0x31]	8844	1			T2	13		T13	6		T18	3
valid_sources[0x32]	8562	1			T2	6		T13	8		T18	4
valid_sources[0x33]	8590	1			T2	25		T10	1		T13	6
valid_sources[0x34]	61759	1			T12	2		T13	4		T18	1
valid_sources[0x35]	8782	1			T2	14		T11	1		T13	3
valid_sources[0x36]	8682	1			T2	5		T10	1		T12	2
valid_sources[0x37]	8477	1			T2	7		T13	11		T18	3
valid_sources[0x38]	8623	1			T2	16		T13	4		T18	2
valid_sources[0x39]	9978	1			T13	8		T18	3		T21	6
valid_sources[0x3a]	10598	1			T12	2		T13	1		T18	4
valid_sources[0x3b]	8639	1			T2	8		T11	1		T13	11
valid_sources[0x3c]	10529	1			T13	7		T18	3		T21	7
valid_sources[0x3d]	8758	1			T2	13		T13	2		T21	2
valid_sources[0x3e]	9006	1			T2	27		T13	8		T18	3
valid_sources[0x3f]	8960	1			T2	12		T12	1		T13	15
valid_sources[0x40]	8903	1			T13	19		T18	2		T21	3
valid_sources[0x41]	8553	1			T2	4		T13	1		T18	1
valid_sources[0x42]	8722	1			T2	4		T12	2		T13	30
valid_sources[0x43]	8793	1			T11	1		T13	4		T26	10
valid_sources[0x44]	8674	1			T2	27		T12	2		T13	5
valid_sources[0x45]	9104	1			T2	5		T11	1		T13	9
valid_sources[0x46]	9112	1			T2	1		T10	1		T13	15
valid_sources[0x47]	15034	1			T2	12		T10	2		T13	5
valid_sources[0x48]	8630	1			T13	6		T18	10		T26	5
valid_sources[0x49]	9085	1			T13	14		T18	6		T20	1
valid_sources[0x4a]	8514	1			T11	2		T18	4		T26	15
valid_sources[0x4b]	9065	1			T13	2		T18	3		T20	2
valid_sources[0x4c]	8796	1			T2	4		T12	2		T13	12
valid_sources[0x4d]	8697	1			T2	12		T11	1		T13	27
valid_sources[0x4e]	47024	1			T10	1		T12	1		T13	7
valid_sources[0x4f]	9512	1			T18	5		T21	5		T22	8
valid_sources[0x50]	11999	1			T2	2		T10	2		T12	2
valid_sources[0x51]	9052	1			T13	9		T18	1		T26	3
valid_sources[0x52]	9427	1			T2	12		T10	1		T13	4
valid_sources[0x53]	8856	1			T2	9		T10	1		T12	2
valid_sources[0x54]	10653	1			T13	11		T14	1782		T18	9
valid_sources[0x55]	10040	1			T2	4		T12	1		T13	5
valid_sources[0x56]	27860	1			T13	7		T21	3		T22	2
valid_sources[0x57]	8498	1			T2	4		T12	1		T13	14
valid_sources[0x58]	10120	1			T2	14		T3	3		T13	17
valid_sources[0x59]	11261	1			T2	11		T13	9		T18	3
valid_sources[0x5a]	9809	1			T18	3		T21	6		T22	3
valid_sources[0x5b]	41527	1			T2	2		T13	10		T18	5
valid_sources[0x5c]	8432	1			T10	1		T13	19		T18	4
valid_sources[0x5d]	14680	1			T13	13		T21	2		T22	4
valid_sources[0x5e]	8431	1			T2	1		T10	1		T12	3
valid_sources[0x5f]	9570	1			T10	1		T13	6		T18	3
valid_sources[0x60]	8482	1			T2	36		T12	1		T13	4
valid_sources[0x61]	8289	1			T11	2		T12	1		T13	9
valid_sources[0x62]	8863	1			T2	2		T13	13		T18	5
valid_sources[0x63]	75184	1			T13	7		T18	4		T20	2
valid_sources[0x64]	36345	1			T11	1		T13	7		T18	2
valid_sources[0x65]	8410	1			T2	2		T10	2		T12	1
valid_sources[0x66]	8614	1			T2	15		T13	5		T21	10
valid_sources[0x67]	8649	1			T13	4		T18	1		T21	3
valid_sources[0x68]	37988	1			T2	2		T18	3		T21	7
valid_sources[0x69]	11958	1			T13	14		T18	6		T21	5
valid_sources[0x6a]	10059	1			T10	1		T13	5		T18	3
valid_sources[0x6b]	9251	1			T2	14		T12	1		T13	15
valid_sources[0x6c]	8512	1			T2	2		T12	2		T13	18
valid_sources[0x6d]	8907	1			T10	1		T13	8		T18	3
valid_sources[0x6e]	8948	1			T2	9		T13	6		T21	9
valid_sources[0x6f]	8433	1			T10	1		T12	2		T13	3
valid_sources[0x70]	8459	1			T2	11		T10	1		T13	8
valid_sources[0x71]	11527	1			T2	1		T11	1		T13	3
valid_sources[0x72]	10327	1			T2	22		T12	3		T13	2
valid_sources[0x73]	8655	1			T2	6		T12	1		T13	4
valid_sources[0x74]	33732	1			T2	5		T13	17		T18	9
valid_sources[0x75]	39821	1			T2	4		T13	7		T18	3
valid_sources[0x76]	8383	1			T13	5		T18	5		T26	9
valid_sources[0x77]	9702	1			T2	9		T13	2		T26	5
valid_sources[0x78]	10174	1			T13	5		T18	3		T21	6
valid_sources[0x79]	10141	1			T2	7		T13	12		T18	5
valid_sources[0x7a]	8818	1			T2	11		T13	3		T18	3
valid_sources[0x7b]	8617	1			T10	1		T11	2		T13	12
valid_sources[0x7c]	8279	1			T13	10		T18	3		T26	10
valid_sources[0x7d]	11242	1			T10	1		T13	3		T26	8
valid_sources[0x7e]	8281	1			T2	10		T10	2		T12	2
valid_sources[0x7f]	8418	1			T2	4		T13	4		T18	2
valid_sources[0x80]	8496	1			T13	3		T18	1		T26	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1307720

1

T2

350

T3

1

T4

207

values[0x0]

all_enables

biggest_size

140826

1

T2

287

T10

10

T11

8

values[0x1]

all_enables

biggest_size

139309

1

T2

291

T10

6

T11

3