Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	90701853	14565	0	0
claim_transition_if_regwen_rd_A	90701853	1641	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90701853	14565	0	0
T33	86848	0	0	0
T48	0	1	0	0
T49	389418	13	0	0
T71	5465	0	0	0
T90	10401	0	0	0
T93	0	3	0	0
T95	0	17	0	0
T105	21188	0	0	0
T106	137326	0	0	0
T107	183025	0	0	0
T108	8778	0	0	0
T109	12486	0	0	0
T110	2823	0	0	0
T114	0	4	0	0
T115	0	2	0	0
T116	0	15	0	0
T152	0	1	0	0
T153	0	8	0	0
T154	0	2	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90701853	1641	0	0
T32	54271	0	0	0
T33	86848	0	0	0
T46	28646	0	0	0
T48	0	10	0	0
T49	389418	0	0	0
T89	345009	6	0	0
T120	0	15	0	0
T121	0	11	0	0
T122	0	12	0	0
T126	0	1	0	0
T128	0	1	0	0
T155	0	9	0	0
T156	0	16	0	0
T157	0	3	0	0
T158	23982	0	0	0
T159	27279	0	0	0
T160	154162	0	0	0
T161	1172	0	0	0
T162	943	0	0	0