Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2057689	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2279004

1

T1

8

T2

1781

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3989298	1			T2	1789		T3	2		T4	757
values[0x0]	173409	1			T1	21		T2	542		T3	1
values[0x1]	173986	1			T1	27		T2	506		T4	74

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1636499	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2700194

1

T1

16

T2

2007

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13403	1			T2	15		T11	7		T12	1
valid_sources[0x01]	30925	1			T2	12		T11	10		T15	14
valid_sources[0x02]	14092	1			T2	9		T11	8		T15	20
valid_sources[0x03]	20233	1			T2	11		T6	1		T11	14
valid_sources[0x04]	29058	1			T2	10		T11	1		T15	11
valid_sources[0x05]	12525	1			T2	7		T6	1		T11	10
valid_sources[0x06]	22083	1			T2	11		T6	1		T15	58
valid_sources[0x07]	13374	1			T2	13		T6	1		T15	6
valid_sources[0x08]	14198	1			T1	1		T2	9		T6	2
valid_sources[0x09]	13216	1			T2	13		T11	8		T21	3
valid_sources[0x0a]	17465	1			T2	7		T11	6		T21	1
valid_sources[0x0b]	14328	1			T2	15		T11	10		T15	4
valid_sources[0x0c]	13172	1			T2	8		T6	3		T11	6
valid_sources[0x0d]	15401	1			T2	12		T6	1		T11	7
valid_sources[0x0e]	13572	1			T1	1		T2	7		T11	5
valid_sources[0x0f]	11695	1			T2	18		T6	1		T11	8
valid_sources[0x10]	13571	1			T2	12		T11	5		T21	1
valid_sources[0x11]	14176	1			T2	9		T6	1		T11	4
valid_sources[0x12]	12666	1			T2	13		T6	2		T11	4
valid_sources[0x13]	12519	1			T2	16		T3	2		T6	1
valid_sources[0x14]	12739	1			T2	11		T6	2		T11	8
valid_sources[0x15]	15038	1			T2	9		T11	12		T15	11
valid_sources[0x16]	12634	1			T2	8		T6	1		T11	4
valid_sources[0x17]	15722	1			T2	4		T6	1		T11	9
valid_sources[0x18]	13369	1			T2	18		T11	3		T15	7
valid_sources[0x19]	15384	1			T2	13		T6	1		T11	3
valid_sources[0x1a]	13193	1			T2	11		T6	1		T11	10
valid_sources[0x1b]	12208	1			T2	9		T11	7		T15	7
valid_sources[0x1c]	14839	1			T2	6		T6	1		T11	5
valid_sources[0x1d]	13320	1			T2	8		T11	6		T21	1
valid_sources[0x1e]	12368	1			T2	8		T6	1		T11	3
valid_sources[0x1f]	13781	1			T1	1		T2	8		T11	7
valid_sources[0x20]	14564	1			T1	2		T2	12		T11	3
valid_sources[0x21]	12633	1			T2	12		T11	8		T15	6
valid_sources[0x22]	15780	1			T2	10		T11	1		T15	14
valid_sources[0x23]	14098	1			T2	7		T6	1		T11	12
valid_sources[0x24]	30831	1			T2	5		T11	7		T21	1
valid_sources[0x25]	15342	1			T2	13		T6	1		T11	8
valid_sources[0x26]	12238	1			T1	1		T2	9		T11	6
valid_sources[0x27]	12865	1			T2	11		T6	1		T11	9
valid_sources[0x28]	13502	1			T1	1		T2	6		T6	2
valid_sources[0x29]	12971	1			T2	11		T4	298		T11	1
valid_sources[0x2a]	13016	1			T2	9		T11	9		T15	13
valid_sources[0x2b]	12259	1			T1	2		T2	17		T6	2
valid_sources[0x2c]	11578	1			T2	16		T11	3		T15	22
valid_sources[0x2d]	14047	1			T2	18		T6	1		T11	8
valid_sources[0x2e]	14654	1			T2	12		T4	192		T6	2
valid_sources[0x2f]	13815	1			T2	18		T6	1		T11	5
valid_sources[0x30]	13531	1			T2	11		T6	1		T11	5
valid_sources[0x31]	12714	1			T2	12		T11	4		T15	2
valid_sources[0x32]	13854	1			T2	13		T6	1		T11	13
valid_sources[0x33]	16648	1			T2	9		T6	1		T11	4
valid_sources[0x34]	11953	1			T1	1		T2	9		T11	17
valid_sources[0x35]	15260	1			T2	12		T11	7		T15	5
valid_sources[0x36]	13249	1			T2	8		T6	2		T11	3
valid_sources[0x37]	12803	1			T2	10		T6	1		T11	13
valid_sources[0x38]	14431	1			T2	7		T6	1		T11	4
valid_sources[0x39]	16328	1			T2	8		T11	6		T15	27
valid_sources[0x3a]	12466	1			T2	12		T6	1		T11	1
valid_sources[0x3b]	12942	1			T2	16		T6	2		T11	3
valid_sources[0x3c]	14481	1			T2	10		T6	2		T11	8
valid_sources[0x3d]	12127	1			T1	3		T2	14		T6	2
valid_sources[0x3e]	12882	1			T2	9		T15	7		T22	4
valid_sources[0x3f]	13320	1			T2	13		T6	1		T11	4
valid_sources[0x40]	15632	1			T2	18		T11	4		T15	1
valid_sources[0x41]	13759	1			T2	11		T6	1		T11	2
valid_sources[0x42]	12456	1			T2	15		T6	1		T11	12
valid_sources[0x43]	45618	1			T2	11		T6	1		T11	9
valid_sources[0x44]	13800	1			T2	9		T6	1		T11	3
valid_sources[0x45]	12908	1			T2	8		T11	5		T15	18
valid_sources[0x46]	13851	1			T2	9		T11	8		T15	5
valid_sources[0x47]	13347	1			T2	7		T3	1		T6	3
valid_sources[0x48]	13283	1			T2	13		T4	56		T6	1
valid_sources[0x49]	13749	1			T1	1		T2	5		T6	1
valid_sources[0x4a]	12421	1			T2	7		T11	1		T15	12
valid_sources[0x4b]	13614	1			T2	10		T6	1		T11	5
valid_sources[0x4c]	12167	1			T2	11		T11	3		T15	5
valid_sources[0x4d]	13275	1			T2	8		T11	4		T15	33
valid_sources[0x4e]	12378	1			T2	11		T6	2		T11	2
valid_sources[0x4f]	12863	1			T2	10		T6	3		T11	16
valid_sources[0x50]	12875	1			T2	8		T6	1		T11	8
valid_sources[0x51]	14944	1			T2	7		T11	5		T15	11
valid_sources[0x52]	13397	1			T2	12		T11	9		T12	1
valid_sources[0x53]	14247	1			T1	1		T2	12		T11	1
valid_sources[0x54]	12965	1			T1	2		T2	6		T11	4
valid_sources[0x55]	13288	1			T2	6		T11	1		T15	10
valid_sources[0x56]	13638	1			T2	13		T11	6		T15	24
valid_sources[0x57]	13067	1			T2	8		T11	1		T15	12
valid_sources[0x58]	12561	1			T2	10		T11	5		T15	5
valid_sources[0x59]	12856	1			T2	10		T6	1		T11	10
valid_sources[0x5a]	13148	1			T2	8		T11	9		T15	16
valid_sources[0x5b]	13982	1			T2	19		T6	2		T11	1
valid_sources[0x5c]	12071	1			T2	14		T6	2		T11	3
valid_sources[0x5d]	12853	1			T2	15		T6	1		T11	3
valid_sources[0x5e]	13606	1			T2	10		T6	1		T11	5
valid_sources[0x5f]	21284	1			T2	12		T11	8		T21	1
valid_sources[0x60]	16191	1			T2	18		T11	8		T21	1
valid_sources[0x61]	12289	1			T2	20		T6	1		T11	6
valid_sources[0x62]	26120	1			T2	7		T6	2		T11	5
valid_sources[0x63]	14869	1			T1	4		T2	11		T11	15
valid_sources[0x64]	11941	1			T1	2		T2	9		T11	7
valid_sources[0x65]	13391	1			T2	11		T6	2		T11	7
valid_sources[0x66]	13584	1			T1	3		T2	17		T6	1
valid_sources[0x67]	19112	1			T2	7		T6	1		T11	3
valid_sources[0x68]	12526	1			T2	15		T11	8		T15	14
valid_sources[0x69]	13630	1			T2	16		T6	1		T11	7
valid_sources[0x6a]	15219	1			T2	8		T6	1		T11	11
valid_sources[0x6b]	12697	1			T2	14		T11	8		T15	17
valid_sources[0x6c]	13247	1			T2	14		T11	14		T15	19
valid_sources[0x6d]	24714	1			T2	14		T11	11		T15	4
valid_sources[0x6e]	13304	1			T2	13		T6	3		T11	5
valid_sources[0x6f]	12491	1			T2	11		T11	6		T15	34
valid_sources[0x70]	21240	1			T2	11		T5	1128		T11	6
valid_sources[0x71]	12341	1			T2	5		T6	2		T11	1
valid_sources[0x72]	13340	1			T2	12		T11	8		T15	8
valid_sources[0x73]	14491	1			T2	9		T11	2		T21	1
valid_sources[0x74]	12166	1			T2	12		T11	5		T12	3
valid_sources[0x75]	14395	1			T2	14		T6	2		T11	14
valid_sources[0x76]	12147	1			T2	11		T11	1		T21	1
valid_sources[0x77]	12672	1			T2	15		T6	1		T11	3
valid_sources[0x78]	13753	1			T2	10		T11	4		T15	18
valid_sources[0x79]	12423	1			T2	9		T11	3		T15	2
valid_sources[0x7a]	15003	1			T2	13		T11	4		T15	20
valid_sources[0x7b]	14370	1			T2	6		T6	2		T11	1
valid_sources[0x7c]	12409	1			T2	11		T6	2		T11	5
valid_sources[0x7d]	13672	1			T2	9		T6	1		T11	6
valid_sources[0x7e]	11994	1			T2	14		T4	9		T6	1
valid_sources[0x7f]	13755	1			T2	10		T6	1		T11	10
valid_sources[0x80]	13775	1			T2	12		T6	1		T11	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1979196

1

T2

856

T3

2

T4

377

values[0x0]

all_enables

biggest_size

150477

1

T1

6

T2

469

T4

60

values[0x1]

all_enables

biggest_size

149331

1

T1

2

T2

456

T4

63