Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	106261492	15600	0	0
claim_transition_if_regwen_rd_A	106261492	1014	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106261492	15600	0	0
T17	277608	2	0	0
T44	34059	0	0	0
T49	11096	0	0	0
T90	0	3	0	0
T91	0	17	0	0
T102	8201	0	0	0
T103	25790	0	0	0
T104	1517	0	0	0
T105	91120	0	0	0
T109	0	6	0	0
T146	0	10	0	0
T147	0	14	0	0
T148	0	15	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	13945	0	0	0
T153	54450	0	0	0
T154	2079	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106261492	1014	0	0
T28	39599	0	0	0
T90	363529	5	0	0
T111	0	51	0	0
T112	0	15	0	0
T149	0	2	0	0
T151	0	4	0	0
T155	0	7	0	0
T156	0	1	0	0
T157	0	9	0	0
T158	0	13	0	0
T159	0	4	0	0
T160	2497	0	0	0
T161	16742	0	0	0
T162	2739	0	0	0
T163	921	0	0	0
T164	23807	0	0	0
T165	38247	0	0	0
T166	8471	0	0	0
T167	2921	0	0	0