Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1615456	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1833645

1

T1

5

T2

4478

T3

844

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3111449	1			T2	8819		T3	819		T4	154
values[0x0]	168162	1			T1	17		T2	45		T3	267
values[0x1]	169490	1			T1	14		T2	38		T3	253

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1282474	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2166627

1

T1

7

T2

5383

T3

948

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10064	1			T2	30		T3	11		T13	8
valid_sources[0x01]	12522	1			T2	31		T3	7		T5	2
valid_sources[0x02]	10113	1			T2	37		T3	4		T5	2
valid_sources[0x03]	12256	1			T2	34		T3	6		T5	1
valid_sources[0x04]	10254	1			T2	29		T3	5		T13	8
valid_sources[0x05]	11240	1			T2	34		T3	1		T5	7
valid_sources[0x06]	10368	1			T2	35		T3	2		T13	6
valid_sources[0x07]	9864	1			T2	31		T3	2		T5	1
valid_sources[0x08]	11727	1			T2	37		T3	5		T5	1
valid_sources[0x09]	10037	1			T2	38		T3	5		T5	7
valid_sources[0x0a]	9967	1			T1	1		T2	29		T3	6
valid_sources[0x0b]	9976	1			T2	36		T3	3		T13	6
valid_sources[0x0c]	10222	1			T2	32		T3	6		T5	1
valid_sources[0x0d]	10169	1			T2	38		T3	3		T5	6
valid_sources[0x0e]	30306	1			T2	33		T3	2		T5	3
valid_sources[0x0f]	12301	1			T1	1		T2	38		T3	4
valid_sources[0x10]	9628	1			T2	29		T3	5		T5	4
valid_sources[0x11]	10313	1			T2	38		T3	8		T5	1
valid_sources[0x12]	13140	1			T1	1		T2	28		T3	4
valid_sources[0x13]	10214	1			T2	39		T3	9		T13	20
valid_sources[0x14]	11858	1			T2	41		T3	7		T13	12
valid_sources[0x15]	10068	1			T2	41		T3	7		T13	4
valid_sources[0x16]	88906	1			T2	27		T3	3		T5	1
valid_sources[0x17]	10418	1			T2	35		T3	4		T5	1
valid_sources[0x18]	9827	1			T2	25		T3	9		T5	2
valid_sources[0x19]	10926	1			T1	1		T2	30		T3	5
valid_sources[0x1a]	9914	1			T2	37		T3	1		T4	11
valid_sources[0x1b]	10308	1			T2	29		T3	4		T5	2
valid_sources[0x1c]	61423	1			T2	34		T3	6		T13	7
valid_sources[0x1d]	10053	1			T2	36		T3	7		T5	3
valid_sources[0x1e]	9608	1			T1	1		T2	37		T3	2
valid_sources[0x1f]	11504	1			T2	40		T3	4		T13	3
valid_sources[0x20]	10137	1			T2	42		T3	7		T5	2
valid_sources[0x21]	10088	1			T2	28		T3	2		T5	6
valid_sources[0x22]	9991	1			T1	1		T2	40		T3	16
valid_sources[0x23]	11142	1			T2	33		T3	2		T12	1
valid_sources[0x24]	9968	1			T2	34		T3	1		T5	2
valid_sources[0x25]	11004	1			T2	35		T3	5		T13	2
valid_sources[0x26]	10258	1			T2	40		T3	3		T5	2
valid_sources[0x27]	10102	1			T2	35		T3	7		T5	1
valid_sources[0x28]	11011	1			T2	34		T3	11		T13	6
valid_sources[0x29]	10361	1			T2	30		T3	7		T5	3
valid_sources[0x2a]	10125	1			T2	30		T3	3		T5	1
valid_sources[0x2b]	10013	1			T2	39		T3	3		T13	11
valid_sources[0x2c]	12037	1			T2	40		T3	3		T13	4
valid_sources[0x2d]	10010	1			T2	44		T3	11		T13	11
valid_sources[0x2e]	10995	1			T2	35		T3	10		T5	1
valid_sources[0x2f]	9660	1			T2	22		T3	3		T13	6
valid_sources[0x30]	10033	1			T1	2		T2	37		T3	2
valid_sources[0x31]	10373	1			T2	35		T3	2		T5	1
valid_sources[0x32]	10087	1			T2	31		T3	4		T5	1
valid_sources[0x33]	9660	1			T2	22		T3	6		T5	5
valid_sources[0x34]	10128	1			T2	28		T3	5		T5	1
valid_sources[0x35]	9782	1			T2	32		T3	5		T5	3
valid_sources[0x36]	10109	1			T2	30		T3	3		T5	2
valid_sources[0x37]	9703	1			T2	45		T3	9		T13	7
valid_sources[0x38]	36032	1			T2	41		T3	4		T5	3
valid_sources[0x39]	10614	1			T2	30		T3	6		T5	2
valid_sources[0x3a]	10027	1			T2	32		T3	7		T5	2
valid_sources[0x3b]	10043	1			T2	37		T3	3		T5	1
valid_sources[0x3c]	10101	1			T2	41		T3	2		T13	13
valid_sources[0x3d]	9881	1			T2	22		T3	2		T13	7
valid_sources[0x3e]	15268	1			T1	1		T2	26		T3	9
valid_sources[0x3f]	9936	1			T2	35		T3	11		T4	10
valid_sources[0x40]	9798	1			T2	40		T3	3		T5	2
valid_sources[0x41]	10814	1			T2	44		T3	3		T5	4
valid_sources[0x42]	9806	1			T2	31		T3	1		T4	1
valid_sources[0x43]	10119	1			T2	35		T3	3		T13	4
valid_sources[0x44]	10183	1			T2	35		T3	3		T5	2
valid_sources[0x45]	10069	1			T2	39		T3	3		T13	2
valid_sources[0x46]	9914	1			T2	33		T3	5		T13	13
valid_sources[0x47]	10057	1			T2	52		T3	3		T5	2
valid_sources[0x48]	10124	1			T2	33		T3	4		T5	4
valid_sources[0x49]	10043	1			T2	36		T3	1		T4	67
valid_sources[0x4a]	9950	1			T2	29		T3	1		T5	1
valid_sources[0x4b]	10016	1			T2	33		T3	1		T5	1
valid_sources[0x4c]	10416	1			T2	44		T3	7		T13	7
valid_sources[0x4d]	9770	1			T2	35		T3	5		T5	5
valid_sources[0x4e]	9612	1			T2	34		T3	7		T5	1
valid_sources[0x4f]	33847	1			T2	27		T3	4		T4	5
valid_sources[0x50]	10625	1			T2	37		T3	4		T5	3
valid_sources[0x51]	10177	1			T2	32		T3	9		T5	2
valid_sources[0x52]	9905	1			T2	35		T3	2		T5	6
valid_sources[0x53]	10937	1			T2	34		T3	3		T5	2
valid_sources[0x54]	10092	1			T2	22		T3	6		T5	2
valid_sources[0x55]	10227	1			T2	29		T3	7		T13	2
valid_sources[0x56]	12502	1			T2	40		T3	9		T5	4
valid_sources[0x57]	9786	1			T2	47		T3	1		T5	4
valid_sources[0x58]	10286	1			T2	33		T3	4		T5	3
valid_sources[0x59]	10307	1			T2	38		T3	7		T5	7
valid_sources[0x5a]	12388	1			T2	35		T3	2		T5	1
valid_sources[0x5b]	10726	1			T2	37		T3	4		T5	4
valid_sources[0x5c]	11052	1			T2	37		T3	6		T5	2
valid_sources[0x5d]	9870	1			T2	40		T3	11		T13	9
valid_sources[0x5e]	10919	1			T2	44		T3	5		T5	1
valid_sources[0x5f]	12678	1			T2	34		T3	6		T5	2
valid_sources[0x60]	10433	1			T2	34		T3	6		T5	1
valid_sources[0x61]	10034	1			T2	34		T3	10		T5	1
valid_sources[0x62]	10419	1			T2	35		T3	4		T5	1
valid_sources[0x63]	9871	1			T2	23		T3	8		T13	5
valid_sources[0x64]	10114	1			T1	1		T2	38		T3	6
valid_sources[0x65]	9939	1			T2	37		T3	3		T5	1
valid_sources[0x66]	9702	1			T2	44		T3	2		T5	4
valid_sources[0x67]	10161	1			T2	40		T3	5		T5	2
valid_sources[0x68]	9743	1			T2	34		T3	8		T5	2
valid_sources[0x69]	9675	1			T2	29		T3	2		T5	2
valid_sources[0x6a]	10197	1			T2	38		T3	6		T5	2
valid_sources[0x6b]	62911	1			T2	33		T3	6		T5	2
valid_sources[0x6c]	9783	1			T2	29		T3	4		T5	2
valid_sources[0x6d]	10347	1			T1	1		T2	32		T3	5
valid_sources[0x6e]	10345	1			T1	1		T2	48		T3	4
valid_sources[0x6f]	11540	1			T2	34		T3	12		T5	5
valid_sources[0x70]	10265	1			T2	37		T3	4		T13	6
valid_sources[0x71]	12396	1			T2	38		T3	3		T13	8
valid_sources[0x72]	10900	1			T2	36		T3	4		T5	2
valid_sources[0x73]	10043	1			T2	35		T3	4		T5	3
valid_sources[0x74]	9926	1			T2	22		T3	7		T13	6
valid_sources[0x75]	17877	1			T2	35		T3	5		T5	3
valid_sources[0x76]	10057	1			T2	28		T3	10		T5	2
valid_sources[0x77]	10347	1			T2	38		T3	6		T5	1
valid_sources[0x78]	12120	1			T2	42		T3	4		T5	4
valid_sources[0x79]	10072	1			T2	35		T3	7		T5	1
valid_sources[0x7a]	10164	1			T2	35		T3	6		T13	2
valid_sources[0x7b]	10329	1			T2	40		T3	7		T5	8
valid_sources[0x7c]	28406	1			T2	43		T3	6		T13	9
valid_sources[0x7d]	10243	1			T2	33		T3	6		T13	4
valid_sources[0x7e]	11360	1			T2	30		T3	2		T5	1
valid_sources[0x7f]	10057	1			T2	42		T3	1		T5	1
valid_sources[0x80]	10147	1			T2	28		T3	7		T13	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1541977

1

T2

4411

T3

388

T4

66

values[0x0]

all_enables

biggest_size

146220

1

T1

2

T2

37

T3

241

values[0x1]

all_enables

biggest_size

145448

1

T1

3

T2

30

T3

215