Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	100.00	82.35	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	103273441	16704	0	0
claim_transition_if_regwen_rd_A	103273441	1126	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103273441	16704	0	0
T19	0	2	0	0
T26	342572	4	0	0
T27	68000	0	0	0
T28	374903	0	0	0
T47	0	18	0	0
T63	16061	0	0	0
T65	45945	0	0	0
T89	0	21	0	0
T91	0	5	0	0
T93	1424	0	0	0
T94	1285	0	0	0
T95	5507	0	0	0
T96	1371	0	0	0
T97	26163	0	0	0
T119	0	13	0	0
T153	0	1	0	0
T154	0	4	0	0
T155	0	15	0	0
T156	0	2	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103273441	1126	0	0
T98	0	4	0	0
T115	110794	10	0	0
T131	0	22	0	0
T146	0	130	0	0
T147	0	136	0	0
T148	0	23	0	0
T157	0	35	0	0
T158	0	56	0	0
T159	0	5	0	0
T160	0	13	0	0
T161	27088	0	0	0
T162	1369	0	0	0
T163	7786	0	0	0
T164	201333	0	0	0
T165	65666	0	0	0
T166	24048	0	0	0
T167	1230	0	0	0
T168	25867	0	0	0
T169	41286	0	0	0