Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2418984	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2647745

1

T2

1186

T3

6

T4

13359

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4710366	1			T2	1372		T3	75		T4	25505
values[0x0]	177670	1			T2	313		T3	2		T4	460
values[0x1]	178693	1			T2	303		T3	6		T4	419

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1924702	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3142027

1

T2

1357

T3

29

T4

16021

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21183	1			T2	9		T4	88		T9	19
valid_sources[0x01]	17524	1			T2	3		T3	2		T4	98
valid_sources[0x02]	15874	1			T2	2		T4	113		T9	10
valid_sources[0x03]	16055	1			T2	4		T4	88		T9	6
valid_sources[0x04]	16476	1			T2	5		T4	102		T9	13
valid_sources[0x05]	60209	1			T2	24		T4	110		T9	9
valid_sources[0x06]	17882	1			T2	9		T4	115		T9	9
valid_sources[0x07]	16180	1			T2	9		T3	2		T4	97
valid_sources[0x08]	32134	1			T2	13		T4	98		T9	3
valid_sources[0x09]	15963	1			T2	17		T4	106		T9	5
valid_sources[0x0a]	16611	1			T3	1		T4	106		T9	1
valid_sources[0x0b]	16334	1			T2	19		T4	103		T9	10
valid_sources[0x0c]	17280	1			T2	4		T4	112		T9	16
valid_sources[0x0d]	26553	1			T2	1		T4	111		T9	13
valid_sources[0x0e]	36854	1			T2	15		T4	105		T9	8
valid_sources[0x0f]	19063	1			T2	9		T4	99		T9	11
valid_sources[0x10]	15929	1			T2	3		T4	96		T9	7
valid_sources[0x11]	15425	1			T4	117		T9	2		T12	10
valid_sources[0x12]	15970	1			T2	17		T3	1		T4	111
valid_sources[0x13]	16385	1			T4	90		T9	3		T12	4
valid_sources[0x14]	15731	1			T2	9		T4	107		T9	10
valid_sources[0x15]	19124	1			T2	10		T3	1		T4	119
valid_sources[0x16]	15562	1			T2	1		T4	108		T9	7
valid_sources[0x17]	16113	1			T2	5		T3	2		T4	112
valid_sources[0x18]	16423	1			T2	6		T4	106		T9	4
valid_sources[0x19]	15572	1			T2	11		T3	2		T4	94
valid_sources[0x1a]	17141	1			T2	2		T4	115		T9	5
valid_sources[0x1b]	15723	1			T2	11		T4	108		T9	5
valid_sources[0x1c]	16508	1			T2	12		T4	83		T9	2
valid_sources[0x1d]	73842	1			T2	3		T3	4		T4	108
valid_sources[0x1e]	16046	1			T2	4		T3	1		T4	110
valid_sources[0x1f]	15973	1			T2	8		T4	94		T9	3
valid_sources[0x20]	15710	1			T4	98		T9	8		T12	6
valid_sources[0x21]	17151	1			T2	4		T4	118		T9	9
valid_sources[0x22]	34492	1			T2	3		T4	93		T9	4
valid_sources[0x23]	16071	1			T2	15		T4	103		T9	8
valid_sources[0x24]	16147	1			T2	5		T4	98		T9	6
valid_sources[0x25]	16125	1			T2	11		T3	1		T4	100
valid_sources[0x26]	17998	1			T2	16		T4	124		T9	5
valid_sources[0x27]	15672	1			T2	9		T4	106		T9	3
valid_sources[0x28]	16011	1			T2	3		T4	95		T10	1
valid_sources[0x29]	18362	1			T2	16		T4	104		T9	14
valid_sources[0x2a]	17889	1			T2	2		T4	91		T9	2
valid_sources[0x2b]	16983	1			T2	10		T4	109		T9	9
valid_sources[0x2c]	89815	1			T2	5		T4	107		T9	8
valid_sources[0x2d]	15488	1			T2	30		T4	86		T9	8
valid_sources[0x2e]	16771	1			T2	2		T4	113		T9	1
valid_sources[0x2f]	16127	1			T2	3		T4	114		T9	8
valid_sources[0x30]	17556	1			T2	3		T3	1		T4	100
valid_sources[0x31]	16047	1			T2	3		T4	99		T9	11
valid_sources[0x32]	15964	1			T4	97		T9	14		T10	5
valid_sources[0x33]	15673	1			T2	6		T4	132		T9	5
valid_sources[0x34]	15699	1			T2	9		T4	126		T9	7
valid_sources[0x35]	17914	1			T3	3		T4	121		T9	2
valid_sources[0x36]	15748	1			T4	109		T9	2		T10	2
valid_sources[0x37]	16062	1			T2	8		T4	95		T9	13
valid_sources[0x38]	16051	1			T2	18		T4	120		T9	1
valid_sources[0x39]	17460	1			T2	14		T3	1		T4	98
valid_sources[0x3a]	16203	1			T4	103		T9	12		T12	6
valid_sources[0x3b]	15931	1			T2	14		T4	96		T9	15
valid_sources[0x3c]	17056	1			T2	5		T4	99		T9	4
valid_sources[0x3d]	16211	1			T4	114		T9	2		T12	9
valid_sources[0x3e]	16296	1			T2	2		T4	100		T9	10
valid_sources[0x3f]	16715	1			T2	7		T4	98		T9	9
valid_sources[0x40]	17971	1			T2	6		T3	4		T4	94
valid_sources[0x41]	60973	1			T2	12		T4	93		T9	2
valid_sources[0x42]	15866	1			T2	6		T3	2		T4	79
valid_sources[0x43]	17485	1			T2	9		T4	109		T9	17
valid_sources[0x44]	16642	1			T2	5		T4	98		T9	11
valid_sources[0x45]	16386	1			T2	15		T4	91		T9	4
valid_sources[0x46]	17688	1			T2	3		T4	102		T9	5
valid_sources[0x47]	16040	1			T2	9		T4	100		T9	7
valid_sources[0x48]	15666	1			T2	9		T4	92		T9	5
valid_sources[0x49]	54306	1			T2	9		T4	94		T9	11
valid_sources[0x4a]	17206	1			T2	2		T4	103		T9	3
valid_sources[0x4b]	16512	1			T4	103		T9	2		T10	1
valid_sources[0x4c]	16367	1			T2	3		T3	1		T4	91
valid_sources[0x4d]	15956	1			T2	9		T3	2		T4	120
valid_sources[0x4e]	15982	1			T2	9		T4	110		T9	4
valid_sources[0x4f]	15697	1			T2	2		T4	107		T9	14
valid_sources[0x50]	15777	1			T2	10		T4	111		T9	6
valid_sources[0x51]	15704	1			T2	15		T4	81		T9	1
valid_sources[0x52]	17689	1			T2	10		T4	113		T9	8
valid_sources[0x53]	16120	1			T4	106		T9	5		T10	6
valid_sources[0x54]	16008	1			T4	101		T12	7		T14	12
valid_sources[0x55]	16987	1			T2	2		T4	119		T9	5
valid_sources[0x56]	16142	1			T2	3		T4	92		T9	7
valid_sources[0x57]	15529	1			T2	3		T4	95		T9	9
valid_sources[0x58]	15739	1			T2	1		T4	116		T10	15
valid_sources[0x59]	77719	1			T2	6		T4	116		T9	3
valid_sources[0x5a]	15786	1			T2	3		T3	1		T4	117
valid_sources[0x5b]	18470	1			T2	14		T3	1		T4	108
valid_sources[0x5c]	17875	1			T2	3		T4	108		T9	4
valid_sources[0x5d]	16663	1			T2	1		T4	104		T9	10
valid_sources[0x5e]	15689	1			T2	5		T3	1		T4	125
valid_sources[0x5f]	15698	1			T2	8		T4	106		T9	6
valid_sources[0x60]	15368	1			T2	29		T4	120		T9	11
valid_sources[0x61]	15582	1			T4	95		T9	7		T12	7
valid_sources[0x62]	18860	1			T2	21		T4	115		T9	9
valid_sources[0x63]	15687	1			T2	2		T4	108		T9	5
valid_sources[0x64]	15904	1			T2	8		T4	106		T9	8
valid_sources[0x65]	15682	1			T2	6		T3	5		T4	124
valid_sources[0x66]	53433	1			T2	2		T4	105		T9	13
valid_sources[0x67]	15564	1			T2	9		T4	117		T9	9
valid_sources[0x68]	15629	1			T2	5		T3	1		T4	105
valid_sources[0x69]	16211	1			T2	14		T4	90		T9	1
valid_sources[0x6a]	17725	1			T2	14		T3	1		T4	115
valid_sources[0x6b]	15876	1			T2	11		T4	106		T9	6
valid_sources[0x6c]	16906	1			T2	8		T4	108		T9	4
valid_sources[0x6d]	21809	1			T2	9		T4	101		T9	8
valid_sources[0x6e]	16364	1			T4	116		T9	18		T10	7
valid_sources[0x6f]	18004	1			T2	9		T3	1		T4	104
valid_sources[0x70]	15785	1			T2	4		T4	88		T9	18
valid_sources[0x71]	16060	1			T2	32		T4	92		T9	10
valid_sources[0x72]	16001	1			T2	6		T4	109		T9	8
valid_sources[0x73]	15787	1			T2	17		T4	96		T9	9
valid_sources[0x74]	16008	1			T2	3		T4	96		T9	3
valid_sources[0x75]	15649	1			T2	1		T4	89		T9	2
valid_sources[0x76]	17405	1			T2	3		T4	108		T9	17
valid_sources[0x77]	15965	1			T2	16		T4	119		T9	3
valid_sources[0x78]	15769	1			T2	1		T4	107		T9	6
valid_sources[0x79]	16554	1			T2	1		T4	97		T9	25
valid_sources[0x7a]	15762	1			T2	14		T4	98		T9	1
valid_sources[0x7b]	16013	1			T2	5		T4	104		T9	4
valid_sources[0x7c]	16128	1			T2	5		T4	104		T9	5
valid_sources[0x7d]	16226	1			T2	5		T4	115		T9	7
valid_sources[0x7e]	15431	1			T2	5		T4	114		T9	5
valid_sources[0x7f]	15583	1			T2	14		T3	1		T4	92
valid_sources[0x80]	16054	1			T2	8		T3	1		T4	100

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2340609

1

T2

650

T4

12585

T9

471

values[0x0]

all_enables

biggest_size

153982

1

T2

276

T3

1

T4

401

values[0x1]

all_enables

biggest_size

153154

1

T2

260

T3

5

T4

373