Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	100.00	82.35	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	119764361	16013	0	0
claim_transition_if_regwen_rd_A	119764361	1296	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119764361	16013	0	0
T8	12301	0	0	0
T41	553635	3	0	0
T68	0	2	0	0
T82	0	2	0	0
T83	0	6	0	0
T147	0	7	0	0
T148	0	4	0	0
T149	0	15	0	0
T150	0	5	0	0
T151	0	5	0	0
T152	0	7	0	0
T153	40342	0	0	0
T154	38745	0	0	0
T155	51298	0	0	0
T156	1247	0	0	0
T157	43395	0	0	0
T158	67313	0	0	0
T159	28306	0	0	0
T160	28627	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119764361	1296	0	0
T43	32837	0	0	0
T54	6612	0	0	0
T68	0	5	0	0
T82	479744	3	0	0
T118	0	29	0	0
T129	0	78	0	0
T138	0	74	0	0
T142	0	53	0	0
T151	0	14	0	0
T161	0	22	0	0
T162	0	7	0	0
T163	0	78	0	0
T164	21611	0	0	0
T165	9104	0	0	0
T166	30385	0	0	0
T167	1680	0	0	0
T168	2039	0	0	0
T169	106940	0	0	0
T170	24020	0	0	0