Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1356362	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1581296

1

T1

972

T2

1113

T3

1029

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2586551	1			T1	827		T2	1043		T3	1141
values[0x0]	174783	1			T1	314		T2	373		T3	275
values[0x1]	176324	1			T1	350		T2	331		T3	285

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1075224	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1862434

1

T1

1093

T2

1246

T3

1175

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9937	1			T1	5		T3	15		T14	1
valid_sources[0x01]	11023	1			T1	11		T2	2		T14	1
valid_sources[0x02]	9968	1			T1	5		T3	18		T12	5
valid_sources[0x03]	9666	1			T2	15		T3	3		T14	6
valid_sources[0x04]	10167	1			T1	6		T2	12		T13	1
valid_sources[0x05]	9858	1			T1	6		T2	1		T3	1
valid_sources[0x06]	11078	1			T1	9		T2	15		T3	1
valid_sources[0x07]	9746	1			T1	9		T3	3		T14	1
valid_sources[0x08]	27827	1			T1	4		T3	3		T13	1
valid_sources[0x09]	9934	1			T1	5		T3	12		T14	2
valid_sources[0x0a]	9793	1			T1	9		T3	9		T13	1
valid_sources[0x0b]	10143	1			T1	7		T3	10		T13	3
valid_sources[0x0c]	9908	1			T1	13		T2	27		T3	14
valid_sources[0x0d]	11314	1			T1	10		T3	2		T11	890
valid_sources[0x0e]	10261	1			T1	10		T3	1		T13	3
valid_sources[0x0f]	9748	1			T1	6		T2	3		T3	3
valid_sources[0x10]	17991	1			T1	8		T2	5		T3	2
valid_sources[0x11]	10258	1			T1	7		T2	16		T3	11
valid_sources[0x12]	9843	1			T1	5		T3	7		T12	3
valid_sources[0x13]	9684	1			T1	9		T2	10		T3	3
valid_sources[0x14]	10052	1			T1	8		T3	3		T12	3
valid_sources[0x15]	10027	1			T1	4		T2	7		T14	1
valid_sources[0x16]	9879	1			T1	2		T20	2		T30	4
valid_sources[0x17]	10171	1			T1	7		T2	13		T3	1
valid_sources[0x18]	10947	1			T1	9		T2	16		T3	3
valid_sources[0x19]	10082	1			T1	3		T2	20		T3	16
valid_sources[0x1a]	10019	1			T1	4		T12	1		T13	1
valid_sources[0x1b]	10431	1			T1	2		T3	2		T12	1
valid_sources[0x1c]	9827	1			T1	3		T2	4		T12	2
valid_sources[0x1d]	9710	1			T1	4		T3	18		T14	2
valid_sources[0x1e]	11636	1			T1	1		T2	13		T3	4
valid_sources[0x1f]	9671	1			T1	6		T3	1		T14	2
valid_sources[0x20]	10427	1			T1	5		T2	9		T12	3
valid_sources[0x21]	11240	1			T1	7		T3	27		T12	3
valid_sources[0x22]	9833	1			T1	3		T3	8		T12	1
valid_sources[0x23]	10355	1			T1	6		T2	8		T3	1
valid_sources[0x24]	10354	1			T1	10		T2	20		T13	2
valid_sources[0x25]	11170	1			T1	8		T3	18		T14	3
valid_sources[0x26]	17299	1			T1	6		T3	1		T14	3
valid_sources[0x27]	9912	1			T1	10		T2	9		T14	3
valid_sources[0x28]	11607	1			T1	5		T20	8		T30	11
valid_sources[0x29]	9857	1			T1	11		T2	6		T3	1
valid_sources[0x2a]	9907	1			T1	6		T2	16		T3	1
valid_sources[0x2b]	9969	1			T1	5		T2	11		T3	6
valid_sources[0x2c]	10332	1			T1	3		T2	13		T3	7
valid_sources[0x2d]	10301	1			T1	7		T14	1		T20	11
valid_sources[0x2e]	9997	1			T1	13		T2	5		T3	16
valid_sources[0x2f]	11758	1			T1	7		T12	1		T13	1
valid_sources[0x30]	10316	1			T1	14		T3	4		T12	6
valid_sources[0x31]	9695	1			T1	3		T14	2		T20	1
valid_sources[0x32]	13745	1			T1	5		T2	7		T3	23
valid_sources[0x33]	11529	1			T1	5		T2	16		T3	2
valid_sources[0x34]	10149	1			T1	6		T2	21		T3	5
valid_sources[0x35]	9946	1			T1	6		T2	16		T3	11
valid_sources[0x36]	9852	1			T1	4		T2	12		T3	1
valid_sources[0x37]	13541	1			T1	4		T2	31		T3	20
valid_sources[0x38]	13872	1			T1	4		T2	4		T20	7
valid_sources[0x39]	9995	1			T1	4		T2	4		T3	10
valid_sources[0x3a]	11753	1			T1	10		T2	3		T3	2
valid_sources[0x3b]	10073	1			T1	5		T2	8		T3	1
valid_sources[0x3c]	10083	1			T1	10		T3	10		T14	2
valid_sources[0x3d]	10052	1			T1	5		T3	12		T12	5
valid_sources[0x3e]	12412	1			T1	5		T3	3		T20	5
valid_sources[0x3f]	13238	1			T1	9		T3	2		T13	1
valid_sources[0x40]	9933	1			T1	9		T2	2		T3	11
valid_sources[0x41]	9733	1			T1	3		T3	27		T14	3
valid_sources[0x42]	11951	1			T1	3		T2	6		T3	4
valid_sources[0x43]	9810	1			T1	6		T2	28		T3	5
valid_sources[0x44]	11064	1			T1	5		T2	20		T3	2
valid_sources[0x45]	9923	1			T1	5		T3	12		T12	6
valid_sources[0x46]	10131	1			T1	8		T2	1		T3	9
valid_sources[0x47]	9798	1			T1	3		T2	18		T13	1
valid_sources[0x48]	15742	1			T1	9		T2	13		T3	16
valid_sources[0x49]	34926	1			T1	5		T3	1		T12	3
valid_sources[0x4a]	12883	1			T1	7		T3	8		T14	1
valid_sources[0x4b]	9909	1			T1	5		T3	7		T12	6
valid_sources[0x4c]	9786	1			T1	5		T2	1		T3	2
valid_sources[0x4d]	10099	1			T1	6		T2	23		T3	29
valid_sources[0x4e]	13337	1			T1	9		T2	12		T3	2
valid_sources[0x4f]	12186	1			T1	7		T2	4		T3	23
valid_sources[0x50]	13717	1			T1	6		T3	9		T14	4
valid_sources[0x51]	12270	1			T1	3		T2	16		T3	2
valid_sources[0x52]	9783	1			T1	3		T3	1		T13	1
valid_sources[0x53]	10028	1			T1	3		T2	6		T3	6
valid_sources[0x54]	10019	1			T1	4		T12	2		T20	10
valid_sources[0x55]	9761	1			T1	4		T2	20		T12	1
valid_sources[0x56]	9989	1			T1	5		T3	18		T12	6
valid_sources[0x57]	20399	1			T1	2		T2	2		T3	17
valid_sources[0x58]	14241	1			T1	7		T2	3		T3	16
valid_sources[0x59]	9883	1			T1	5		T3	7		T12	3
valid_sources[0x5a]	10075	1			T1	5		T12	3		T14	2
valid_sources[0x5b]	9808	1			T1	5		T2	4		T3	8
valid_sources[0x5c]	11406	1			T1	2		T3	11		T20	4
valid_sources[0x5d]	11215	1			T1	4		T2	3		T3	13
valid_sources[0x5e]	10336	1			T1	6		T2	21		T14	3
valid_sources[0x5f]	9741	1			T1	7		T2	8		T12	2
valid_sources[0x60]	11198	1			T1	5		T2	8		T13	1
valid_sources[0x61]	10139	1			T1	1		T2	7		T3	5
valid_sources[0x62]	10320	1			T1	6		T2	53		T3	7
valid_sources[0x63]	9962	1			T1	5		T2	9		T20	15
valid_sources[0x64]	10189	1			T1	10		T2	8		T3	1
valid_sources[0x65]	9807	1			T1	2		T3	1		T12	2
valid_sources[0x66]	11725	1			T1	8		T2	9		T12	1
valid_sources[0x67]	10057	1			T1	7		T2	23		T3	4
valid_sources[0x68]	14756	1			T1	10		T2	22		T3	7
valid_sources[0x69]	17042	1			T1	6		T2	22		T3	1
valid_sources[0x6a]	9901	1			T1	4		T3	3		T12	3
valid_sources[0x6b]	9710	1			T1	3		T2	12		T3	2
valid_sources[0x6c]	10018	1			T1	6		T12	1		T13	2
valid_sources[0x6d]	10047	1			T1	3		T2	2		T12	3
valid_sources[0x6e]	9912	1			T1	2		T3	11		T12	1
valid_sources[0x6f]	9926	1			T1	3		T2	5		T3	23
valid_sources[0x70]	10073	1			T1	3		T2	9		T3	10
valid_sources[0x71]	11118	1			T1	8		T3	1		T20	3
valid_sources[0x72]	9632	1			T1	5		T2	4		T14	1
valid_sources[0x73]	9758	1			T1	6		T2	20		T3	15
valid_sources[0x74]	9885	1			T1	8		T2	3		T3	1
valid_sources[0x75]	10015	1			T1	7		T3	1		T14	3
valid_sources[0x76]	9973	1			T1	7		T2	16		T3	2
valid_sources[0x77]	9885	1			T1	7		T2	8		T3	2
valid_sources[0x78]	12342	1			T1	6		T3	7		T13	1
valid_sources[0x79]	9814	1			T1	5		T3	7		T14	3
valid_sources[0x7a]	10100	1			T1	7		T3	1		T14	2
valid_sources[0x7b]	10288	1			T1	6		T2	10		T3	6
valid_sources[0x7c]	13518	1			T1	5		T2	26		T3	1
valid_sources[0x7d]	9919	1			T1	6		T14	3		T20	9
valid_sources[0x7e]	103746	1			T1	11		T3	3		T14	3
valid_sources[0x7f]	9682	1			T1	6		T2	46		T3	2
valid_sources[0x80]	11060	1			T1	4		T2	18		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1278389

1

T1

387

T2

493

T3

536

values[0x0]

all_enables

biggest_size

151713

1

T1

282

T2

332

T3

237

values[0x1]

all_enables

biggest_size

151194

1

T1

303

T2

288

T3

256